JPH0555895B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram control device built into an information processing device.

[Technical Background of the Invention] Conventionally, in information processing devices, there have been two types of interrupt processing: interrupt processing that occurs in relation to (synchronously) execution of an instruction, and interrupt processing that occurs unrelated to (asynchronous) execution of an instruction. be. The former type of interrupt processing includes instruction parity errors that occur before the instruction is executed, over-address interrupts (occurs when attempting to execute the contents of an address larger than the main memory on which it is implemented), etc. , arithmetic overflow interrupts that occur during or after the execution of an instruction, and stack instruction error (errors that occur when an operation reaches outside the stack area) interrupts.The latter interrupt processing involves interrupts from channels and timers. There is.

FIG. 2 is a block diagram showing an example of a conventional microprogram control device. instruction register 1
In this example, the instruction 100 fetched from the main memory (not shown) is set, and the OP which is part of the instruction is set.
Code 200 is given to the instruction decoding ROM 2 as an address. Further, the instruction 100 in the instruction register 1 is output to the interrupt detection circuit 3. A microprogram start address is read from the instruction decoding ROM 2 according to the OP code 200 and output to the multiplexer 4. The interrupt detection circuit 3 is a circuit that detects an error that causes an interrupt, an address match function used for debugging, etc. from the contents of the instruction register 1 (instruction 100), and detects an interrupt factor such as an address match function used for debugging. request signal 4
Outputs 00. The interrupt control circuit 5 determines priorities and holds interrupt information for various interrupt factors, and generates an interrupt processing start address for a microprogram. A signal 500 is input, and a microprogram interrupt processing start address 600 is output to the multiplexer 4. Note that the interrupt processing start address 600 is assigned a start address corresponding to each interrupt factor. Furthermore, the interrupt control circuit 5 outputs a switching signal 700 to the multiplexer 4 indicating that there is an interrupt. Multiplexer 4 selects either address 300 or 600 by signal 700 and outputs it to multiplexer 6. The multiplexer 6 selects the address of the multiplexer 4 each time one instruction is completed, and selects the address 800 output from the address control circuit 7 when executing an instruction requiring several steps in a microprogram. The selected address is outputted by multiplexer 6 to control storage circuit 9 via driver 8 . The control storage circuit 9 stores a microprogram,
A microinstruction is read from the address corresponding to the address output from the multiplexer 6, and is transferred to a register (CDR: control data register) 10.
is set to The contents 1000 of the address control field of the microprogram 900, which are part of the data held in the register 10, are output to the address control circuit 7.

[Problems with the background art] In the above conventional microprogram control device,
An interrupt request signal 400 synchronized with the instruction and an interrupt cause signal 500 asynchronous with the instruction are input to the interrupt control circuit 5, and a synchronized interrupt determined in preprocessing of instruction execution, for example, the parity of the instruction Errors etc.
They were handled and processed in the same way as asynchronous interrupts, such as interrupts from channels and timers. In other words, although the output start addresses are different for synchronous and asynchronous interrupts, the configuration performs the phase matching required for synchronous interrupt processing, regardless of whether the output is synchronous or asynchronous. was adopted. In other words, synchronous interrupts are handled by replacing the start address output from the instruction decode ROM 2 with the start address for interrupt processing.
This process of replacing the start address for interrupt processing was also used for asynchronous interrupts. On the other hand, phase adjustment is not necessary for asynchronous interrupts, and quick processing of the interrupts is required. However, when there is only one interrupt control circuit, even in the case of asynchronous interrupts, the above-mentioned phase adjustment is performed, resulting in a delay in the processing of the interrupts.
In addition, in the case of a device that undergoes pipeline processing, for example, an instruction decoding ROM 2 and a multiplexer 4
Insert two latches between multiplexer 4 and
When one latch is inserted between the instruction decoding ROM 2 and the multiplexer 6 to divide the circuit into four stages, the interrupt control circuit 5 also has a phase corresponding to the two latches inserted between the instruction decoding ROM 2 and the multiplexer 4. Since the start address of the microprogram for asynchronous interrupts is latched in the same way as the start address for synchronous interrupts, processing for asynchronous interrupts is further delayed. I decided to do it. Furthermore, since the processing addresses for synchronous and asynchronous interrupts are output from the same interrupt control circuit 5, a special circuit must be provided to distinguish between synchronous and asynchronous interrupts. , it was not possible to accurately separate and execute recovery processing from interrupts. In other words, assuming the worst case when an asynchronous interrupt occurs for any level of interrupt, recovery after an interrupt is executed by returning to (resetting) the beginning of the previous processing. was. As a result, unnecessary resets are performed, resulting in a problem of inefficient processing.

[Object of the Invention] The present invention was made to solve the problems of the conventional microprogram control device described above, and its purpose is to solve the problems of the conventional microprogram control device. An object of the present invention is to provide a microprogram control device that can separate interrupts and perform appropriate processing according to each interrupt.

[Summary of the Invention] The microprogram control device of the present invention comprises an instruction register in which an instruction including an OP code is fetched from a main memory, an interrupt generated in connection with the execution of the instruction, and an interrupt generated in connection with the execution of the instruction. a control memory circuit storing a microprogram for processing in response to an interrupt that occurs regardless of the instruction and a microprogram for processing the instruction fetched into the instruction register; and an OP of the instruction fetched into the instruction register.
an instruction decoding ROM that decodes the code and outputs the start address of the corresponding microprogram in the control circuit; and an interrupt that outputs an interrupt request signal when necessary based on the instruction fetched into the instruction register. a detection circuit; a first interrupt control circuit that outputs a start address of a microprogram related to a corresponding interrupt process in the control circuit in response to an interrupt request signal output from the interrupt detection circuit; a second interrupt control circuit that receives an interrupt cause signal related to an interrupt that occurs regardless of execution of the instruction and outputs a start address of a microprogram related to the corresponding interrupt processing in the control circuit; a first multiplexer that selects either the output of the decoding ROM or the output of the first interrupt control circuit; and the address selected by the first multiplexer and the output of the second interrupt control circuit. a second multiplexer for selecting either one, the first interrupt control circuit is configured to respond to the first interrupt request signal output from the interrupt detection circuit;
The second interrupt control circuit controls switching of the second multiplexer in accordance with the interrupt factor signal.

[Embodiment of the Invention] FIG. 1 is a block diagram showing an embodiment of a microprogram control device of the present invention. An embodiment of the present invention will be described below with reference to the drawings, in which the same parts as those of the conventional example are given the same reference numerals. Instruction 100 fetched from main memory (not shown) is set in instruction register IR1. OP code 200 which is part of the contents loaded into instruction register 1
is output to the instruction decoding ROM 2, and the instruction 100 in the instruction register 1 is output to the interrupt detection circuit 3. The start address 300 of the microprogram corresponding to the OP code 200 is read from the instruction decoding ROM 2 and is input to the multiplexer MUX11. Interrupt detection circuit 3
outputs an interrupt request signal 400 to the synchronous interrupt control circuit (first interrupt control circuit) 12 when necessary based on the contents of the instruction 100. The synchronous interrupt control circuit 12 outputs a microprogram interrupt processing start address 1100 corresponding to the interrupt request signal 400 to the multiplexer 11, and also outputs a multiplexer switching signal 1200 to the multiplexer 11. Multiplexer 11 receives switching signal 120
0, selects either address 300 or 1100 and outputs it to multiplexer 4.

The interrupt factor signal 500, which is generated asynchronously with respect to the execution of the instruction 100, is generated by an asynchronous interrupt control circuit (second
(interrupt control circuit) 13. This asynchronous interrupt control circuit 13 determines priorities and holds interrupt information, and the input interrupt cause signal 5
A microprogram interrupt processing start address 1300 corresponding to 00 is generated, and this microprogram interrupt processing start address 1300 is output to the multiplexer 4. The asynchronous interrupt control circuit 13 also sends the switching signal 700 to the multiplexer 4.
The multiplexer 4 outputs this signal 700 to
Based on this, either the address from the multiplexer 11 or the address from the asynchronous interrupt control circuit 13 is selected and output to the multiplexer 6.

The multiplexer 6 selects the address on the multiplexer 4 side each time execution of one instruction is completed, and when executing an instruction that requires several steps, selects the address 800 output from the address control circuit 7, and transfers the selected address to the driver 8. It is output to the control storage circuit 9 via. The control storage circuit 9 outputs a microinstruction 90 based on the signal from the multiplexer 6.
0 is read and set in register CDR10. Contents 10 of the address control field of the microinstruction 900 set in register 10
00 is input to the address control circuit 7, and the address control circuit 7 outputs the address 800 to the multiplexer 6 based on this.

Next, the operation of this embodiment will be explained. In the case of normal instruction execution, an instruction 100 fetched from main memory (not shown) is loaded into the instruction register 1, and then decoding is started for this instruction 100. That is, the instruction decoding ROM 2 decodes the OP code 200 input from the instruction register 1 and outputs the start address 300 of the microprogram assigned to the instruction 100. This starting address 300 is multiplexer 1
1 and 4 to access the control storage circuit 9. In the control storage circuit 9, the microinstruction 900 is read out based on the input start address 300, and this is set in the register 10, so that execution of the instruction 100 is started.

When execution of the instruction starts, the multiplexer 6 outputs the output from the address control circuit 7 (address 80).
0) is selected, and the control memory circuit 9 is accessed one after another in response to this signal to execute several steps of instructions. When the execution of the instruction is completed, the multiplexer 6 is switched to select the output of the multiplexer 4, and the execution of the next instruction is started. Note that during the normal instruction execution, the multiplexer 11 is switched to select the output of the instruction decoding ROM 2, and the multiplexer 4 is switched to select the output of the multiplexer 11.

Here, instruction 1 set in instruction register 1
Assuming that a parity error occurs in the instruction 00, this instruction 100 should not be executed, and a hardware abnormality interrupt process must be performed. That is, in this case, from the instruction 100 to the interrupt detection circuit 3
When detecting a parity error, an interrupt request signal 400 for processing this parity error is output to the synchronous interrupt control circuit 12. Synchronous interrupt control circuit 1
2, an interrupt processing start address for parity error processing is generated based on the interrupt request signal 400, and this interrupt processing start address 1100 is sent to the control storage circuit 9 via multiplexers 11, 4, and 6. to access. At this time, the multiplexer 11 is switched to select the synchronous interrupt control circuit 12 side by the switching signal 1200 outputted by the synchronous interrupt control circuit 12. In the control storage circuit 9,
A microinstruction 900 based on the interrupt processing start address 1100 is read out and is stored in register 1.
By being loaded to 0, parity error processing is executed.

Next, the instruction 10 is sent to the asynchronous interrupt control circuit 13.
When an interrupt factor signal 500 that is asynchronous with the execution of 0 is input, the asynchronous interrupt control circuit 13 outputs the interrupt processing start address 1300 of the microprogram corresponding to the input interrupt factor signal 500. The starting address 1300 accesses the control storage circuit 9 via multiplexers 4,6.
At this time, the multiplexer 4 is switched to select the output signal of the asynchronous interrupt control circuit 13 by the switching signal 700 output from the asynchronous interrupt control circuit 13. The control storage circuit 9 stores a microinstruction 900 based on the start address 1300.
is read out and set in the register 10, thereby executing the interrupt process corresponding to the interrupt cause signal 500.

Thus, in this embodiment, interrupts that occur in connection with the execution of an instruction and interrupts that occur unrelated to the execution of an instruction are separated, and the interrupt processing microprogram is controlled by a different interrupt control circuit. The starting address will be output. And the start address of the microprogram for synchronous interrupts is
The signal is output from the synchronous interrupt control circuit 12 and is sent to the multiplexer 11 under the control of the synchronous interrupt control circuit 12.
It is replaced with the address output from the instruction decode ROM 2. At this time, due to the synchronization interruption, phase matching for replacement is possible. In addition, in the case of pipeline processing equipment,
For example, a latch can be provided between the instruction decoding ROM 2 and the multiplexer 11, between the multiplexer 11 and the multiplexer 4, and between the multiplexer 4 and the multiplexer 6, so that the structure is divided into four stages. Therefore, the start address of a microprogram for a process corresponding to an asynchronous interrupt only needs to be delayed by the latch provided between multiplexers 4 and 6, and the start address of a microprogram for a process corresponding to an asynchronous interrupt is only delayed by the latch provided between multiplexers 4 and 6. In addition to reducing the degree of delay in processing of instructions,
Ensures proper pipeline processing for output from ROM2. Furthermore, in the case of synchronous interrupts,
The starting address of the corresponding microprogram is
is output from the synchronous interrupt control circuit 12, and is output to the multiplexer 1 under the control of the synchronous interrupt control circuit 12.
1, it is sufficient to replace the address output from the instruction decode ROM 2. On the other hand, in the case of an asynchronous interrupt, it is necessary to perform a reset after the execution of the microprogram for interrupt processing is completed, and to start processing related to the previous instruction from the beginning. In this embodiment, the interrupt control circuit to which the start address of the microprogram is output distinguishes between synchronous interrupts and asynchronous interrupts is the synchronous interrupt control circuit 1.
2 or the asynchronous interrupt control circuit 13. For synchronous interrupts, unnecessary resets are not performed at the time of recovery, and the response to synchronous interrupts and instruction execution are adjusted accordingly. The efficiency of such processing can be improved.

[Effects of the Invention] As explained above, according to the present invention, the interrupt control circuit is divided into two parts depending on whether an interrupt occurs in relation to an instruction or regardless of an instruction. 1. Since the output of the interrupt control circuit is selected between the output of the instruction decode ROM and the output of the instruction decode ROM by the second multiplexer, the instruction decode
ROM output can be replaced at the required position, allowing accurate phase alignment when an instruction occurs in conjunction with an interrupt, and quick execution of interrupt processing when an interrupt occurs unrelated to an instruction. Secured. Furthermore, the cause of the interrupt can be identified by the interrupt control circuit, and the processing upon recovery from the interrupt processing can be easily and appropriately divided and executed. That is, it is possible to perform appropriate processing for interrupts that occur in connection with the execution of instructions and interrupts that occur unrelated to the execution of instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microprogram control device of the present invention, and FIG. 2 is a block diagram showing an example of a conventional microprogram control device. 1... Instruction register, 2... ROM for instruction decoding, 3... Interrupt detection circuit, 4,
6, 11... Multiplexer, 7... Address control circuit, 9... Control storage circuit, 10... Register, 12... Synchronous interrupt control circuit, 13... Asynchronous interrupt control circuit.

Claims (1)

[Scope of Claims] 1. An instruction register in which an instruction including an OP code is fetched from a main memory, an interrupt that occurs in connection with the execution of the instruction, and an interrupt that occurs regardless of the execution of the instruction. a control memory circuit storing a microprogram for processing according to the instruction and a microprogram for processing the instruction fetched into the instruction register; and an OP of the instruction fetched into the instruction register.
an instruction decoding ROM that decodes the code and outputs the start address of the corresponding microprogram in the control circuit; and an interrupt that outputs an interrupt request signal when necessary based on the instruction fetched into the instruction register. a detection circuit; a first interrupt control circuit that outputs a start address of a microprogram related to a corresponding interrupt process in the control circuit in response to an interrupt request signal output from the interrupt detection circuit; a second interrupt control circuit that receives an interrupt cause signal related to an interrupt that occurs regardless of execution of the instruction and outputs a start address of a microprogram related to the corresponding interrupt processing in the control circuit; a first multiplexer that selects either the output of the decoding ROM or the output of the first interrupt control circuit; and the address selected by the first multiplexer and the output of the second interrupt control circuit. a second multiplexer for selecting either one, the first interrupt control circuit is configured to respond to the first interrupt request signal output from the interrupt detection circuit;
A microprogram control device, wherein the second interrupt control circuit controls switching of the second multiplexer according to the interrupt factor signal.