JPH011038A - Control memory error correction control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram control device in an information processing device, and in particular, a function for detecting and correcting a correctable error and inhibiting operation of an arithmetic circuit when an error is detected. The present invention relates to an error correction control method for a control memory comprising:

[Conventional technology]

Conventionally, various types of control memory error correction control systems detect correctable errors in all fields of microinstructions, inhibit updating of the microinstruction register in the clock cycle in which the error is detected, and at the same time stop the operation of the arithmetic circuit. The structure is designed to prevent

[Problem to be solved by the invention]

In the case of the above-mentioned conventional control memory error correction side '<111 method, correctable errors are detected for all fields of microinstructions, and operation suppression is performed to suppress the operation of the arithmetic circuit in the clock cycle in which the error is detected. sending out a signal. However, in this case, the operation inhibit signal to the arithmetic circuit has a large time delay (statically, since the arithmetic circuit is physically separated from the microprogram controller), and as a result, the clock cycle of the microprogram controller There is a problem in that it is limited.

[Means to solve the problem]

The control memory error correction control method according to the present invention, when a correctable error is detected in a field that controls the operation of an arithmetic circuit of a microinstruction, sends an operation inhibit signal to the arithmetic circuit in the clock cycle in which the error is detected; When a correctable error is detected in the field containing the next A1:1 NOS information and error correction code of the microinstruction, an operation inhibit signal is sent to the arithmetic circuit at a timing one clock cycle later than the clock cycle in which the error was detected. It was designed to do so.

[Effect]

Therefore, according to the present invention, it is possible to minimize the time delay of the operation inhibit signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The microprogram control device shown in FIG. 1 includes a control memory 1, a microinstruction register 2, an error detection and correction circuit 3, inhibition signal generation circuits 4 and 5, a branch address save register 7, an address save register 8, a +1 counter 9, Increment address register 10, return address register 11, return address stack 12,
Address selection circuit 13, return address selection circuit 14
, a selection circuit 15, and a control circuit 16.

An error correction code based on a Hamming code is added to the microinstruction stored in the control memory 1, and the microinstruction is stored in the control B memory 1 with this correction code added. The microinstruction read from the control memory 1 is then set in the microinstruction register 2.

This microinstruction register contains next address information, and the contents of the microinstruction register 2 update the return address register 11 and return address stack 12, control the return address selection circuit 14, and further control the return address selection circuit 14. The address source of the control memory I is determined by the address information from the address selection circuit 13, which is controlled by the control circuit 16, which determines the address of the next microinstruction to be executed according to the contents of 2, and branch address information, which will be described later. Microinstructions are read out one after another starting from 1.

Microinstruction register 2 by error detection and correction circuit 3
When a correctable error is detected in the data sent to the microinstruction register 2, the operation of the arithmetic circuit 6 is inhibited by the inhibition signal from the inhibition signal generation circuit 5. After correcting the error, the inhibit signal is released. In this case, the iJj operation inhibition signal sent to the arithmetic circuit 6 is limited to the field that controls the operation of the arithmetic circuit 6, so as to keep the time delay to a minimum. That is, when the error detection and correction circuit 3 detects a correctable error in the field that controls the operation of the arithmetic circuit 6, the inhibition signal generation circuit 4 outputs the second inhibition signal, and the inhibition signal generation circuit 5 outputs the third inhibition signal. Inhibit signals are sent simultaneously, and the arithmetic circuit 6, microinstruction register 2, branch address save register 7, address save register 8, increment address register 10, return address register 11, and return address stack 12 are activated in the clock cycle in which the error is detected. After the update is inhibited and the error is corrected by the error detection and correction circuit 3, the error in the microinstruction register 2 is corrected as described above, and the second inhibition signal and the third inhibition signal are simultaneously released.

On the other hand, when the error detection and correction circuit 3 detects a correctable error in the field containing the next address information and error correction code of the microinstruction, the inhibition signal generation circuit 4 sends out a second inhibition signal to correct the error. Detected black,
The updating of the microinstruction register 2, address save register 8, increment address register 10, return address register Il, and return address stack 12 is inhibited in one clock cycle; A signal is sent, and updating of the branch address save register 7 and arithmetic circuit 6 is suppressed.

By the way, as described above, since the update of the arithmetic circuit 6 is inhibited by a signal delayed by one clock cycle, when the arithmetic circuit 6 updates a branch instruction, the branch address information indicated by the processing result may be lost. Therefore, if the processing in the arithmetic circuit 6 is performed normally and the branch instruction is executed,
The selection circuit 15 selects the branch address from the arithmetic circuit 6. - On the other hand, when an error is detected in the microinstruction immediately after the branch instruction is executed by the arithmetic circuit 6, the selection circuit 15 selects the branch address save register 7. Based on the contents of address save register 8 and branch address save register 7, microinstruction register 2
is updated, the third inhibit signal to the arithmetic circuit 6 is released, and the operation is restarted.

The above operation will be explained using the time chart of FIG. 2.

When a correctable error <+* is issued in the field containing the next address information and error correction code of the microinstruction register 2, the second inhibition signal is sent from the inhibition signal generation circuit 4, and the operation of the error correction sequence starts. . Since the next address information and the error correction code are not involved in controlling the operation of the arithmetic circuit 6, after the flip-flop of the arithmetic circuit 6 is updated, the third inhibition signal is output from the inhibition signal generation circuit 5 with a delay of one clock cycle. Sent out.

After the error in microinstruction register 2 is corrected, the second
The third inhibition signal is canceled and the microinstruction register 2 is updated, and after a delay of (1) clock cycles, the third inhibition signal is canceled and the operation is resumed.

Next, using the time chart in FIG.
The operation when a correctable error occurs simultaneously in the field containing the first inhibit signal caused by the microinstruction register 2, the next address information of the microinstruction register 2, and the error correction code will be described. In this case, execution of the error correction sequence is inhibited until the first inhibition signal is released, and the same operation as described in FIG. 2 is performed from the clock cycle in which the first inhibition signal is released.

As described above, according to the control memory error correction control system according to this embodiment, there is an address save register that sets the address corresponding to the microinstruction sent to the microinstruction register, and a branch address that sets the branch information sent from the arithmetic circuit. When a correctable error is detected in a field containing next address information and an error correction code, which are part of a microinstruction, at the same time as the first inhibit signal caused by the arithmetic circuit is generated, the first generates a second inhibit signal that inhibits the error correction sequence and inhibits updating of the microinstruction register in the clock cycle in which the error is detected;
The error correction sequence is executed at the same time as the inhibition signal of
It operates by updating the microinstruction register after canceling the second inhibit signal based on the contents of the address save register and branch address save register, and canceling the third inhibit signal for the arithmetic circuit after l clock cycle delay. By restarting the operation, the time delay of the operation inhibit signal can be minimized, and therefore, the clock cycle of the microprogram controller can be prevented from being limited.

FIG. 4 is a block diagram showing the configuration of another embodiment of the control memory error correction control system according to the present invention.

In this figure, the same reference numerals as those in FIG. 1 indicate equivalent components, and the explanation thereof will be omitted.

In this method, when a correctable error is detected by the error detection and correction circuit 3 in the field containing the next address information and error correction code of the microinstruction, when the device stop mode signal is "1", the error display flip-flop 18 to stop the device, and when the device stop mode signal is "0", the deterrent signal is sent from the deterrent signal generation circuits 4 and 5, and the microinstruction register 2 and branch address save are sent in the clock cycle in which the error is detected. Updating of the register 7, address save register 8, increment address register 10, return address register 11, and return address stack 12 is inhibited, and updating of the arithmetic circuit 6 is inhibited with a delay of (1) clock cycles.

As described above, according to the control memory error correction control method according to this embodiment, the address save register sets the address corresponding to the microinstruction set in the microinstruction register, and the branch information \U sent from the arithmetic circuit is set. When a correctable error is detected in the field containing the microinstruction's next address information and error correction code, the error display flip-flop is set by the mode switching signal set during initialization. , a mode in which the device is stopped, and an error correction sequence is executed at the same time as the updating of the microinstruction register is inhibited in the clock cycle in which the error is detected, and a signal is generated to inhibit the operation of the arithmetic circuit after a delay of one clock cycle. After the correction is completed, the microinstruction register is updated based on the contents of the address save register and branch address save register, and the inhibit signal to the arithmetic circuit is released, thereby restarting the operation. The time delay of the inhibit signal can be minimized and thus the clock cycles of the microprogram controller can be prevented from being limited.

〔Effect of the invention〕

As explained above, in the present invention, when a correctable error is detected in a field that controls the operation of the arithmetic circuit of a microinstruction, an operation inhibit signal to the arithmetic circuit is sent in the clock cycle in which the error is detected, and When a correctable error is detected in the field containing the next address information and error correction code, an operation inhibit signal is sent to the arithmetic circuit at a timing one clock cycle later than the clock cycle in which the error was detected. , the time delay of the operation inhibit signal can be minimized, thus preventing the clock cycle of the microprogram controller from being limited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of FIG. 1, and FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 2 is a block diagram showing the configuration. 1... Control memory, 2... Micro instruction register,
3... Error detection and correction circuit, 4... Inhibition signal generation circuit, 5... Inhibition signal generation circuit, 6... Arithmetic circuit, 7
...Branch address save register, 8...Address save register, 9...+1 counter, 10...Increment address register, 11...Return address register, 12...Return address stack, 13... - Address selection circuit, 14... Return address selection circuit, 15... Selection circuit, 16... Control circuit, 17... AND circuit, 18... Error display flip-flop.

Claims (1)

[Claims] A control memory that stores microinstructions, a microinstruction register in which data read from the control memory is set, an arithmetic circuit that operates according to the contents of the microinstruction register, and a next execution according to the contents of the microinstruction register. a control circuit that determines the address of a microinstruction to be executed; and a control circuit that assigns and stores an error correction code to the microinstruction stored in the control memory, and performs error detection and correction based on the contents set in the microinstruction register. an error detection and correction circuit that sets a corrected microinstruction in the microinstruction register; and an inhibition signal generation means that generates a signal that suppresses the operation of the arithmetic circuit when a correctable error is detected by the error detection and correction circuit. In a microprogram-controlled data processing device, when a correctable error is detected in a field that controls the operation of a microinstruction arithmetic circuit,
An operation inhibit signal to the arithmetic circuit is sent in the clock cycle in which the error is detected, and when a correctable error is detected in the field containing the next address information and error correction code of the microinstruction, the clock cycle in which the error is detected is 1. A control memory error correction control system characterized in that an operation inhibiting signal is sent to an arithmetic circuit at a timing delayed by a clock cycle.