JPS635784B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a memory management control method in a data processing system having a memory having an error correction function.

(b) Prior Art and Problems As memories become more highly integrated, it has become common to introduce error correction methods into memory systems. The purpose of this error correction is to correct partial data failures that occur due to temporary errors that occur when reading or writing to memory, or that occur while being stored in memory, so that normal data can be obtained. It is something to do. In particular, data in highly integrated memories is said to be subject to data failures with an increasing probability over time due to external environmental factors such as radiation. To solve this problem, it has been implemented to have a circuit that performs error correction by circulating at a cycle within a range in which the number of erroneous bits in one word does not exceed the correction capability of the error correction circuit. On the other hand, when this memory is actually used, correctable errors may be detected. In this case, the read data is used after being corrected, but the original memory contents must either be corrected on the spot or left uncorrected. It had been taken. However, this processing method has the following problems. Immediately executing a correction write to memory at the time of error detection may require changing the instruction execution cycle when such an error occurs;
Control becomes complicated. At the same time, with this processing method, it is difficult to distinguish between errors for which corrective writing would otherwise be useless due to a permanent failure in one element of the memory, so correction cycles are performed indiscriminately. Otherwise, the only option is to completely suppress the correction write cycle.

In addition, in a system that relies only on cyclic error correction without performing correction cycles, errors due to temporary errors that should normally be corrected by writing corrections occur repeatedly, and when these errors are used, the ability to execute instructions deteriorates. do.

(C) Purpose of the Invention The present invention solves the above problem by combining a correctable memory error correction cycle related to processing temporary errors that occur during instruction execution, etc., and a periodic cyclic correction cycle. The purpose is to measure the resolution of problems.

(d) Structure of the Invention In order to achieve the above object, the present invention performs memory reading based on a given address in a data processing system having a memory in which data to be stored is stored in an error-correctable format. an error correction processing unit having a function of correcting correctable error data and writing to memory after correctable error data is detected; a first control circuit that generates an address of the memory; a second control circuit that registers the address when correctable error data in the usage state of the memory is detected in the data processing system; an address selection unit that selects the output address of the second control circuit with priority over the output address of the control circuit of the first control circuit; The present invention is characterized in that error correction write processing is performed based on the address output by the second control circuit.

(e) Examples of the invention Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 shows an example of a conventional data processing system, in which 1 is a memory, 2 is a central processing unit, 3 is an input/output control unit, 4 is a memory management unit, 5 is an error correction control unit, and 6 is a This is a memory patrol control unit. The central processing unit 2 decodes the instructions on the memory 1 and processes the data. Input/output control device 3
In accordance with instructions from the central processing unit 2, data is transferred between the memory 1 and a peripheral device (not shown) using a method such as cycle stealing.

In this example, access to memory 1 is
2 machine cycles when reading, WRITE
(Writing) is performed in three machine cycles. The reason why the cycle time is long in WRITE is that an error correction code is used for the data in memory 1, and the data written to memory 1 is
This is because if all the bits of the word are not included, the remaining part needs to be rewritten by combining the results of reading from memory 1.

In high-density memory, some of the stored data may change with a certain probability over time due to the effects of radiation and the like. The memory management device 4 including the memory patrol control unit 6 sequentially accesses the entire memory 1 within a certain period to correct and write correctable errors, so that temporary errors accumulate and the correction circuit prevent errors that exceed the capabilities of the In the system shown in FIG. 1, when an error within a correctable range is detected during instruction execution or data transfer with peripheral input/output devices, the central processing unit 2 or the input/output control unit 3 is an error correction cycle (similar to the WRITE cycle) after the READ cycle
has been added to correct the error. This is a process that prevents uncorrectable errors by correcting known errors as soon as possible, as well as repeating error correction when the same data is used repeatedly. This is to prevent delays. As mentioned above, the problem with this method is that when a correctable error is detected, the instruction execution cycle is changed to take a correction write cycle, which makes the control complex.
In addition, performance may be degraded in the event of a permanent memory failure within a correctable range.

FIG. 2 is a block diagram of a data processing system according to an embodiment of the present invention, in which 11 is a memory;
12 is a central processing unit, 13 is an input/output control unit, 1
4 is a memory management device, 15 is an error correction control unit, 1
6 is a memory patrol control section, 17 is an address stack, 18 is an address selection section, 19 is a mask register, and 20 is a mask section.

The operation of the embodiment is as follows.

An error in memory read data that occurs while the central processing unit 12 is executing a command operation or while the input/output control unit 13 is transferring data between the memory 11 and an input/output device (not shown) is detected by the central processing unit 12 or When the input/output control device 13 detects the error and determines that the error is correctable, the error address is sent to the memory management device 14. The memory management device 14 sequentially stores the sent failure addresses in the address stack 17.

On the other hand, when no address is registered in the address stack 17, the memory patrol control unit 16 sequentially generates addresses for accessing all areas of the memory 11 according to a predetermined schedule. This address is sent to the error correction control section 15 via the address selection section 18. The error correction control unit 15 reads data from the memory 11 based on the sent address, and if the error data is correctable, it corrects it and rewrites it to the memory 11.

When no address is stored in the address stack 17, addresses are sequentially generated from the memory patrol control unit 16 and error checking and correction processing is performed. is stored,
Addresses within this address stack 17 are selected preferentially by the address selection section 18. As a result, the error correction control section 15 performs error correction write processing on the addresses in the address stack 17, giving priority to the previous schedule of the memory patrol control section 16. When a plurality of addresses are stored in the address stack 17, the addresses are taken out in sequence starting from the latest address, and error correction write processing is executed continuously.

The mask register 19 stores address information of address areas where errors occur particularly frequently, and the mask unit 20 registers the sent address in the address stack 17 according to the contents of the mask register 19. deter. Furthermore, for the address area specified by the mask register 19, the memory patrol control unit 16
The addresses are updated so that correction writing is performed at a shorter cycle than a predetermined schedule. Furthermore, if the bit in which the error occurs is fixed, the memory management device 14 performs processing such as replacing the bit with a spare bit using a circuit section (not shown).

(f) Effects of the invention The effects of implementing the present invention are as follows.

Simplification of error correction cycle The instruction execution cycle is simplified because correction processing for correctable errors can be performed separately from instruction execution. (A correction write cycle does not need to occur during instruction execution.) It is possible to perform optimal processing according to the error occurrence situation.

Depending on the error occurrence situation, it is possible to flexibly execute corrective writing, switching to replacement bits, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional data processing system, and FIG. 2 is a block diagram of an embodiment of the data processing system according to the present invention. In FIG. 2, 11 is a memory, 12 is a central processing unit, 13 is an input/output control unit, 14 is a memory management unit, 15 is an error correction control unit, 16 is a memory patrol control unit, 17 is an address stack, 18
is an address selection section.

Claims (1)

[Claims] 1. In a data processing system having a memory in which data to be stored is stored in an error-correctable format, when correctable error data is detected by reading the memory based on a given address, the error data is corrected. an error correction processing unit having a function of performing memory writing after performing the above;
a first control circuit that generates an address for sequentially reading all areas of the memory at a cycle within a certain period of time; and when correctable error data in the usage state of the memory is detected in the data processing system. a second control circuit that registers the address in the first control circuit; and an address selection section that selects the output address of the second control circuit with priority over the output address of the first control circuit; A memory management control system characterized in that error correction write processing based on the address output by the second control circuit is performed in priority to error correction write processing based on the address output by the circuit.