JPS61269755A - Trouble processing system for microprogram control device - Google Patents

Abstract

PURPOSE:To correct an error in case of one bit trouble regardless of an intermittent trouble or a fixed trouble and to separate and cut a block of a control memory corresponding only in case of several bit troubles by providing an error detecting/correcting circuit. CONSTITUTION:The error detecting/correcting circuit 10 checks whether or not the contents of the output data bitted at control memories 7a and 7b are normal, and corrects the bit error regardless of the intermittent trouble or the fixed trouble when one bit error exists. When the trouble is several bit ones, based upon the output of the trouble address and an address comparator 6a detected by the circuit 10, the trouble generating sub-compartment is divided and the access to a sub-compartment 7-2 is prevented. Namely, the logical address of the microinstruction is modified through a degrade register 1, an address modifying circuit 2a and an address register 3a, to be modified and the access to the sub-compartment 7-2 is prevented. Thus, the block of the corresponding control memory can be separated and cut.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device in a data processing device, and more particularly to a fault handling method for a control memory.

[Conventional technology]

A main memory that stores multiple microinstructions, a control memory that holds some of the microinstructions, and when the control memory is accessed, if a target microinstruction exists on the control memory, it reads it and executes that microinstruction. execute,
In a control memory fault handling method in a microprogram control device equipped with a microprogram control circuit that loads a block containing a necessary microinstruction from main memory if a target microinstruction does not exist, the control memory is divided into multiple blocks. Errors are detected in the read data of the control memory, and the control memory in which the error has occurred is disabled for use in units of blocks.

[Problem that the invention seeks to solve]

When the control memory is divided into multiple blocks and an error is detected in the read data of the control memory, conventional methods cannot distinguish whether the error is an intermittent fault, a fixed fault, a 1-bit fault, or a multi-bit fault. Since the block in which an error was detected is separated without having to do so, the amount of control memory that can be used is drastically reduced, the amount of microprograms that can be resident is reduced, and the probability that the required microprogram exists in control memory is reduced. . For this reason, the number of times the control memory is loaded from the main memory increases, which inevitably causes a decrease in performance. As described above, the problem with conventional control memory fault handling methods is that when any fault is detected, the block is easily separated.

[Means for solving problems]

The purpose of the present invention is to
The object of the present invention is to provide a fault handling method for a microprogram control device that can correct errors in the case of a one-bit fault and isolate a corresponding block of control memory only in the case of a several-bit fault.

The present invention includes a main memory storing a plurality of microinstructions;
a control memory that holds a part of the microinstructions, and when the control memory is accessed, if a target microinstruction exists on the control memory, it is read out, the microinstruction is executed, and the target microinstruction is read out; a microprogram control circuit that loads a block containing a necessary microinstruction from the main memory if the microprogram control circuit does not exist; The present invention is characterized by comprising a circuit that corrects the data when the fault is a one-bit fault, and a circuit that separates the portion of the control memory that includes the faulty part when the fault is a multi-bit fault.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a fault handling method for a microprogram control device according to an embodiment of the present invention. In this embodiment, the control memory has a two-compartment configuration 7a.

7b, and each compartment is divided into two subcompartments 7-1, 7-2 and 7-3°7-4, respectively. Is degrade register 1 control memory? It has the same number of bits as the subcompartments a and 7b, and each bit corresponds to one subcompartment, and "0" indicates that use is prohibited, and "1" indicates that use is possible.

This degrade register is set based on the outputs of the address comparator and error detection/correction circuit, as will be described later. The address modification circuits 2a and 2b modify the logical address of the microinstruction sent via the signal line 12 by the contents of the degrade register 1, and convert it into a real address, thereby modifying the subcompartment that is disabled. The modified address registers 3a and 3b hold the above-mentioned modified address.The address register 4 sends the address to the control memories 7a and 7b via the signal line 13 to the control memories 7a and 7b via the signal line 14. The address arrays 5a, 5b supply microinstruction addresses to the control memory 7.
Holds information for managing microinstructions in a and -1b in units of blocks. address comparator 5a,
'5b detects in which compartment of the control memories 7a and 7b the block designated by the address register 4 exists, or in neither. AND circuits 3a and 3b are address comparators 6a
, 6b are blocked by the output of degrade register 1. The selector circuit 9 selects the compartment hit by the control memories 7a, 7b based on the outputs of the AND circuits 3'+, 8b. The error detection/correction circuit 10 checks whether the output data of the hit control memory is normal or not. If there is a 1-bit error, the error detection/correction circuit 10 detects whether the 1-bit fault is an intermittent fault or a fixed fault. Correct bit errors. The microinstruction register 11 holds error-corrected normal microinstruction data read from the control memories 7a and 7b.

The operation of this embodiment will be explained below. All subcompartments of control memory? -1,7-2,7-3,7
-4 is in the usable state, the addresses stored in the modified address registers 3a, 3b are not modified by the address modification circuits 2a, 'lb, and match the contents stored in the address register 4. Here, it is assumed that an intermittent or fixed 1-bit failure occurs in a part of the subcompartment 7-2. At this time, when the contents of the address register 4 specify a microinstruction in the block loaded into the portion of the control memory 7a where the 1-bit failure has occurred, the contents are read out from the compartment 7a. On the other hand, the address comparator 6a detects from the outputs of the address register 4 and address array 5a that the block specified by the address register 4 exists in the control memory 7a, controls the selector circuit 9 via the AND circuit 8a, and controls the Let them select 7a. The microinstruction read from compartment 7a is sent to error detection/correction circuit 10 via selector circuit 9. This error detection/correction circuit detects a 1-bit error, corrects the error, and stores normal microinstruction data in the microinstruction register 11.

Furthermore, when the above-mentioned failure is not a 1-bit failure but a several-bit failure, the following operation is performed.

The contents read from the control memory 7a are detected by error detection/
Once sent to correction circuit 10, the error detection/correction circuit detects that the fault is a multi-bit fault. The faulty subcompartment is determined based on the faulty address detected in the error detection/correction circuit 10 and the output of the address comparator 6a, and the bit corresponding to that subcompartment in the degrade register 1 is set to "0".

This bit 10' is input to the address modification circuit 2a,
The subcompartment 7-2 is modified by modifying the logical address of the microinstruction sent via the signal line 12, retaining the modified address in the modified address register 3a, and blocking access to the subcompartment 7-2.
-2 is prohibited.

Although one embodiment of the present invention has been described above, the present invention is not limited only to this embodiment, and it goes without saying that various modifications and changes can be made within the scope of the present invention.

〔Effect of the invention〕

As explained above, the present invention is equipped with an error detection/correction circuit, so that in the event of a one-bit failure that is an intermittent or fixed failure, the faulty block can be rewritten and used normally by the error detection/correction circuit. There is no need to separate it, and the number of loads from main memory to control memory can be reduced, which has the effect of improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Degraded registers 2a, 2b...Address modification circuits 3a, 3b...Modified address register 4...
Address registers 5a, 5b... Address arrays 5a, 5b... Comparators 7a, 7b... Control memories 3a, 3b... AND circuit 9... Selector circuit

Claims (1)

[Claims] (1) A main memory that stores a plurality of microinstructions, a control memory that holds some of the microinstructions, and when the control memory is accessed, if the target microinstruction exists on the control memory, it is read out. and a microprogram control circuit that executes the microinstruction and loads a block containing the necessary microinstruction from the main memory if the target microinstruction does not exist. , a circuit that detects a fault in the read data of the control memory and corrects the data when the fault is a one-bit fault; and a part that includes the fault location of the control memory when the fault is a multi-bit fault. A failure handling method for a microprogram control device, characterized by comprising a circuit for disconnecting.