JPS6022773B2 - Storage device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a memory device using a semiconductor memory element.

Recently, problems called soft errors have become a problem in semiconductor memory devices. A soft error is different from a so-called failure caused by a malfunction in hardware, and is an error that occurs even though there is no defect in the hardware. Among these soft errors, an error in which information stored in the case of a semiconductor memory element is reversed due to Q-rays generated from a substrate or the like is particularly problematic. It is known that this soft error due to the Q line is stochastic, and the probability of error occurrence per unit time is generally used as a measure of the strength of the storage element with respect to the Q line. This high probability of error occurrence per unit time means that once information is written to a memory element, it is not rewritten for a long time, and if it is stored, there is a high probability that the information will be reversed. It means that. In conventional storage devices, if the device does not have a 1-bit error correction function, one reversal will cause the storage device to fail, and even if the device has a 1-bit error correction function, two reversals will cause the storage device to fail. If the contents that have been written are stored as they are until the error occurs, there is a drawback that when the information is read out, it becomes an error that cannot be corrected. An object of the present invention is to provide a storage device that can reduce the probability of failure due to soft errors.

In a storage device having a storage array using semiconductor storage elements, the device of the present invention includes a circuit that prohibits external access to the storage device for a predetermined period of time at a predetermined period, and a circuit that indicates a storage location of the storage array. an address generation circuit that generates addresses in a predetermined order; a comparison circuit that compares the address from the address generation circuit with an address externally applied at a time other than the predetermined time; an error detection and correction circuit that detects and corrects errors in data read from the memory array in response to a read operation of the access circuit that performs a write operation to a storage location specified by an address; a register for storing data whose errors have been detected and corrected by an error detection and correction circuit;
The error detection and correction circuit detects and corrects an error in the data read from the address of n, and stores it in the register.
The comparator circuit does not detect an address match between the predetermined time of the th cycle and the predetermined time of the n+1th cycle, or even if a match is detected, an external output instruction is not received. The data in the register is written to the first address of the storage array at the (n+1)th predetermined time when the write operation is completed. address is generated, a match is detected in the comparator circuit at a time between the predetermined time in the n-th cycle and the predetermined time in the n+1-th cycle, and a write operation is performed from the outside. after generating a second address from the address generation circuit, the error detection and correction circuit detects a tampering in the data read from the second address of the storage array at the predetermined time of the (n+1)th period; The present invention is characterized by comprising a circuit for controlling the correction to be stored in the register.

Next, the present invention will be explained in detail with reference to the drawings.

The embodiment of the present invention shown in FIG.
0, an address register 60, an access control circuit 70, a register 1, an address generation circuit 2, a comparison circuit 3, a control circuit 4, a data selection circuit 5, an address selection circuit 6, and a timing circuit (not shown).

Next, the operation of the present invention will be explained in detail with reference to FIGS. 1 and 2. The control circuit 4 allocates time for the operation of the storage device as follows.

In other words, as shown on the time axis t in Fig. 2, the usable time of the device (hereinafter referred to as CPU) that accesses the storage device is ↑2
is divided into unusable time ↑, and allocated. When accessed by the CPU at time 2, in the case of a write operation, the contents of the write data register 20 are sent to the memory array 10 via the data selection circuit 5, and the address is sent to the address register 6.
The contents of 0 are sent via the address selection circuit 6, and in the case of a readout operation, the information at the address specified by the address register 60 is read out and error-corrected by the Hamming error correction detection circuit 50, and then sent to the read data register 40. The access control circuit 70 controls the CP stream to be sent via the CP stream. At time B, one drafting operation or writing operation is performed under the control of the control circuit 4.

When the control signal TR in FIG. 2 is logic "0", it indicates that the CPU cannot access it, and when it is logic "1", it indicates that it is accessible. At time t after time to, address A is generated in the address generation circuit 2, and the control circuit 4
Since the read/write control signal R/W generated at 1 indicates the logic operation instruction R, the information at address A of the storage array 10 is read out, and if there is a correctable error, the Hamming error correction detection circuit 50 detects the error. The corrected data is stored in register 1 and held as rewrite data Do. time 7
2, the address generated by the address generation circuit 2 and the address of the address register 60 that holds the address from the CPU are compared by the comparison circuit 3 every access. The control circuit 4 generates a readout write control signal R/W, and after the start operation is performed at time 7, it is controlled to indicate the write operation instruction W, but during the following time 72, the comparator circuit Address match is reported from 3, and C at that time
When the access request from the PU indicates a write operation,
The issue write control signal R/W is inverted from the write instruction W to the issue instruction R. By the way, at time 72 between times to and t, there is no address match when a write operation is requested from the CPU, so at time 7, which is after time t, a write operation occurs, and the address A from the address generation circuit 2 is The address held in register 1 is the address indicated by
is written.

After the write operation is completed, the address generation circuit 2 generates the address (A11), the read/write control signal R/W becomes the start operation instruction R, and at time 7 after time t2, the address (A11) is generated. ) is read out and stored and held in the register 1 as data D, and the initial write control signal R/W indicates a write operation instruction W. Farewell to time 2
At time t23 within time 72 between C and t3, C
When an address match is detected at the time of a write request from the PU, the logical write control signal R/W is inverted from the write operation instruction W to the read operation instruction R, and the address generation circuit 2 generates the address (A+2). . Therefore, the operation at time d, which follows time ra', becomes a deliberation operation and the address (A
12) information is read out and error corrected, resulting in data D2
It is stored and held in register 1 as .

The behavior of the landlock bee is the same as the behavior described above. As is clear from the above explanation, by generating all the addresses of the storage array 10 in the address generation circuit 2 and performing the above-mentioned read/write operations on all these addresses, the CPU is prevented from writing. In both cases, information is written to all addresses at least once in a fixed period.

Therefore, by setting this cycle within a time period in which the probability that data that has been left unwritten for a long time becomes uncorrectable due to soft errors can be ignored to some extent, the influence of soft errors can be sufficiently reduced.

The present invention has the effect of reducing the influence of soft errors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the present invention. In FIG. 1, 1...Register, 2...Address generation circuit, 3...Comparison circuit, 4...Control circuit, 5...Data selection circuit, 6...Address selection circuit, 10...Storage Array, 20...Write data register, 30...
- Hamming generation circuit, 40...read data register, 5
0... Hamming error correction detection circuit, 60... address register, 70... access control circuit. Multi-Z Zuhatsu / 4

Claims (1)

[Claims] 1. A memory device having a memory array using semiconductor memory elements, which includes a circuit that prohibits external access to the memory device for a predetermined time at a predetermined period, and a predetermined address indicating a storage location of the memory array. an address generation circuit that generates an address in sequence, a comparison circuit that compares the address from this address generation circuit with an address given externally at a time other than the predetermined time, and an address specified by the address from the address generation circuit. an access circuit that performs a read/write operation with respect to a storage location; an error detection and correction circuit that detects and corrects errors in data read from the storage array in response to the read operation of the access circuit; a register for detecting and storing corrected data; and detecting and correcting errors in data read from the first address of the storage array at the predetermined time of the n-th cycle by the error detection and correction circuit. between the predetermined time of the n-th cycle and the predetermined time of the n+1-th cycle, the comparator circuit determines whether or not the addresses match. When a read instruction is given, the data in the register is written to the first address of the storage array at the (n+1)th predetermined time and after this write operation is completed, the data is read from the address generation circuit as the first address. generating a different second address at the predetermined time and n of the nth period;
The comparison circuit detects a match between the +1st period and the predetermined time, and when an external write operation occurs, the address generation circuit generates a second address, and then the n+1th address is generated. and a circuit for controlling the error detection and correction circuit to detect and correct errors in data read from the second address of the storage array at the predetermined time of the cycle, and then to store the data in the register. A storage device characterized by: