JPH03108044A - Storage device - Google Patents

Abstract

PURPOSE:To efficiently rewrite data in a memory by performing the rewrite operation only at the time of detecting correctable error in read data. CONSTITUTION:If correctable one-bit error is detected by the memory access from a CPU, an address register 1 gives an array address 13 to a syndrome array 3. Contents of the register 1, the syndrome register 2, and the array 3 are compared with one another by a comparator 7. When they noncoincidence with one another, a syndrome is newly registered; but when they coincide with one another, an error counter 4 is counted up by +1. Contents of a rewrite bit holder 6 are set to '1' and are held till the end of the rewrite operation. If the value of the counter 4 is equal to or larger than 2, error is reported as fixed trouble to the higher-order CPU, and the value of the holder 6 is set to 0 to exclude the rewrite operation. Otherwise, the rewrite is performed by a rewrite controller 8, and the holder 6 is reset to 0 by a reset signal 14 after the end of write.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to a storage device, and in particular, when a correctable error occurs in the storage device, rewriting control for a memory array after error correction of read data is performed. This invention relates to a storage device with an improved method.

〔overview〕

The present invention provides memory rewriting by performing a rewriting operation only when the correctable error is detected in a storage device equipped with means for correcting a correctable error in read data and rewriting the memory. This allows for efficient writing.

[Conventional technology]

Conventionally, the rewrite control method for this type of storage device is
For example, as shown in the parole rewrite control method shown in FIG.
Access is made from the PU, etc. (step 5ll), and if a correctable error, which is a 1-bit error, is detected in the successive data (step 512), the data after error correction is written to the error detection location (step 513), Make sure there is no error data in the memory array and count up the address in step 514.
), update the timer for constant period calculation Step 5
15), a control method was adopted in which rewrite control was performed in the same way for the next address, and rewrite control was performed for the entire memory array area.

[Problem that the invention seeks to solve]

In the rewrite control method in the conventional storage device mentioned above,
For example, if the fixed cycle interval is set to 16 μs, which is the refresh cycle of DRAM (dynamic random access memory), and there are 16 modules in the memory array,
With 256kbit DRAM, patrolling the entire memory array can be completed in 1 minute, but with 4Mbit it takes 18 minutes and 16MB
With bit, it takes 72 minutes.

However, if the refresh 5 operation and patrol rewrite control are performed at the same time, the operation takes a considerable amount of time, so the CP
Memory accesses from U, etc. will be made to wait, resulting in a drop in system performance. Therefore, it is necessary to lengthen the periodic interval of rewrite control, and there is a drawback that it takes a very long time to complete patrolling the entire memory array.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device having a rewrite control method that can efficiently rewrite memory by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a storage device equipped with rewriting means for correcting correctable errors in read data and rewriting the data.
The rewriting means includes a syndrome storage means for registering and storing a fault address indicating a fault location and a syndrome indicating a fault bit position as a set when a correctable error is detected; an error count storage means for counting and storing the number of times an error has occurred; a rewrite bit setting means for setting a rewrite bit indicating whether or not an error has been rewritten corresponding to each set registered in the syndrome storage means; Rewriting control means for instructing rewriting when a rewriting bit is set in the rewriting bit setting means and a value of the number of error occurrences stored in the error count storage means is smaller than a predetermined value. It is characterized by containing.

[Effect]

When a correctable error is detected, the fault address and syndrome are registered and stored as a set in the syndrome storage means. Then, the number of times the error occurs is counted and stored by the error count storage means. - In the Expo write bit setting means, a rewrite bit is set corresponding to each set registered and stored in the syndrome storage means.

When a correctable error is detected, the rewrite control means controls the rewrite control means when the rewrite bit is set in the first stage of the rewrite bit cellar and the number of error occurrences registered in the error count storage means is, for example, 1. Then, give a rewrite instruction.

Therefore, rewriting is performed only when a correctable error is detected, making it possible to improve the efficiency of rewriting.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, the fault address 11 when a correctable error occurs is
The contents of address register 1 and syndrome register 2 are set as one set, and when a correctable error occurs, syndrome array 3 and syndrome register 2 are registered. An error counter 4 registers the number of errors occurring for each of the contents of the array 3, an adder 5 counts up the contents of the error counter 4, and a rewrite bit indicating whether rewrite control has been completed is set. It includes a rewrite bit holder 6, a comparator 7 that compares whether the error that has occurred has occurred before and is registered in the syndrome array 3, and a rewrite control 88 that performs rewrite control.

The characteristics of the present invention are as shown in FIG.
A comparator 7, a rewrite bit holder 6 as a rewrite bit holding means, and a rewrite control section 8 as a rewrite control means are provided.

Next, the rewrite control operation of this embodiment will be explained with reference to the flowchart shown in FIG.

When a 1-bit error, which is a correctable error, is detected in memory access from the CPU or the like (step S1), address register 1 gives array address 13 to the syndrome array, and the address register 1, syndrome register 2, and syndrome array 3 are The contents are compared with the comparator 7 (Step S2), and if there is no matching contents, the contents of the address register 1 and syndrome register 2 are newly registered in the syndrome array 3 (Step S3.55)) If they match, the contents of the error count register 4 are ``l
” and increases the count value by one (step S3
．． 34). Then, the contents of rewrite bit register 6 are changed to “
1'' and held until the rewriting operation is completed (step 36). At this time, if the value of the error count register 4 is "2" or more (step S7), it is reported as a fixed fault to the host device such as the CPU (step S9).
, and also sets the contents of the rewrite pit register 6 to "0" and excludes it from subsequent rewrite operations. The rewriting operation is performed in the rewriting control unit 8, and is performed in synchronization with a certain periodic interval, for example, a refreshment period (step 38). After the rewrite operation is completed, the corresponding rewrite pit register 6
is reset to "0" by the reset signal 14 (step 510).

〔Effect of the invention〕

As described above, the present invention provides the following effects by performing a rewrite operation only when a correctable error is detected.

(1) Rewriting control is made more efficient, the frequency of waiting for memory access from the CPU, etc. is extremely reduced, and system performance is not degraded.

(2) Rewriting to erase errors in the memory array improves system reliability.

(3) In the case of a fixed error, by excluding it from rewrite control, there is no need to perform a wasteful rewrite operation, so that the performance of the system is not degraded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. FIG. 2 is a flowchart showing the operation. FIG. 3 is a flowchart showing the operation of the conventional example. 1... Address register, 2... Syndrome register, 3... Syndrome array, 4... Error counter, 5... Adder, 6... Rewrite bit holder, 7... Comparison Equipment, death... Rewriting control section, 11...
・Fault address, 12...Syndrome, 13...
Array address, 14... Reset signal, 81-31
0.311-315...step. Figure 1 Figure

Claims (1)

[Scope of Claims] 1. In a storage device equipped with rewriting means for correcting a correctable error in read data and rewriting the data, the rewriting means: upon detecting a correctable error, generates a fault address indicating the location of the fault. syndrome storage means for registering and storing a syndrome indicating a fault bit position as a set; error count storage means for counting and storing the number of error occurrences for each set registered in the syndrome storage means; and the syndrome storage means a rewrite bit setting means for setting a rewrite bit indicating whether rewriting has been performed for the error corresponding to each set registered in the rewrite bit setting means; and a rewrite bit is set in the rewrite bit setting means, 1. A storage device comprising: rewrite control means for instructing rewriting when the number of error occurrences stored in the count storage means is smaller than a predetermined value.