JPS59168997A - Method of main memory patrolling of computer - Google Patents

Abstract

PURPOSE:To complete main memory patrolling in a short time by connecting a 1 bit error flag and an error address register to a main memory, holding 1 bit error detected during arithmetic processing in the register and allowing CPU to detect an error easily when main memory patrolling which is carried out periodically. CONSTITUTION:A 1 bit error flag 25 connected to an error detecting and correcting section 23 and an error address register 26 connected to an address register 21 are incorporated in SCU2 and input to a patrol controlling section 12 incorporated in CPU1 respectively. The 1 bit error flag 25 is normally in off state, and made on when data reading is made when arithmetic processing is made by CPU1 and when the error detecting and correcting section 23 detects 1 bit error, and informs of presence of 1 bit error in main memory patrolling. Further, the error address register 26 holds an address in which the error concerned is present when a bit error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for correcting errors in a main memory of a computer, and particularly to a method for correcting errors in the main memory with quick and simple operations.

(2) Background of the Technology In the main memory of a computer, main memory patrol is performed in order to improve the reliability of the main memory. this is,
It temporarily suspends normal processing in the central processing unit (hereinafter referred to as CPU), reads the main memory using a patrol signal, detects errors, and corrects and overwrites any errors to correct soft errors. On the other hand, if there is a burst error due to a fixed mechanical failure, the error is corrected by switching to a replacement chip, thereby improving the reliability of the main memory. This type of main memory patrol is performed in the form of an interrupt by temporarily suspending the normal processing operations by the CPU, which is the original work of the computer, that is, the arithmetic processing performed under the control of the O8 (operating system). During that time, the computer is placed in a state not unlike an inactive state.

Therefore, in order to make effective use of the computer, it is desirable that the time required for main memory patrol be as short as possible.

(3) Prior Art and Problems FIG. 1 is a diagram showing an example of a block diagram of a conventional main memory patrol. In this figure, numeral 1 is the CPU, numeral 2 is 80U (storage control unit),
Reference numeral 3 indicates an MSU (main storage unit). The CPU 1 includes a memory access section 11, a patrol control section 12,
It has a timer 13 that starts and stops the patrol control section 12.

The ECU 2 includes an address register 21, a check bit generation section 22, an error detection and correction section n, and a chip replacement control section 24. The memory access unit 11 mediates memory access requests from a normal calculation unit (not shown), the patrol control unit 12, and the like. The patrol control unit 12 issues a control signal for performing main memory patrol, and performs main memory patrol. Address register 2H1
, specifies the storage location of the MSU where the data used for the calculation is to be stored. The check bit generating section 22 is connected to the memory access section 11 and adds an FCC (error check and correct) bit to the write data when writing data from the CPU 1 to the MSU 3. In addition, the error detection and correction unit B
Detect and correct errors or detect 2-bit errors in MSU 3. Furthermore, when the error detection and correction unit B detects a burst error in the MSU 3, the chip replacement control unit 24 receives a signal from the patrol control unit 12 and controls chip replacement within the MSU 3.

For example, as shown in FIG. 2, the MSU 3 stores data divided into addresses of several hundred kilometers or more in the vertical direction, and horizontally stores each data into a predetermined number of bits (
For example, 64 bits), and ECC bits added by the check bit generator 22 at the time of data writing are arranged in parallel at the ends of each data.

In such a configuration example, when the computer performs normal arithmetic processing, memory access is performed from O8, etc., and data at a predetermined address (assumed A) is read, but if a 1-bit error occurs during this read access. If so, the error detection and correction unit n detects the error of the address A) (A1
) is detected, corrected, and sent to CPU 1, where arithmetic processing is performed.

On the other hand, when performing main memory patrol, an interrupt signal is output from the timer 13 and the normal arithmetic processing of O8 is stopped, while a control signal from the patrol control unit 12 is used to perform main memory patrol, that is, error detection of MSU3. , corrections are made. In this main memory C) roll, 0PUI! Based on the signal from the patrol control unit 12, data is read out sequentially for all addresses of MSU3, and if there is a 1-bit error A in the data, the error is corrected by the error detection correction unit n of 5CU2. Then rewrite the correct data to the same address.

By the way, in such a main memory patrol method, all data written to the MSU 3 is patrolled by covering the entire main memory.

However, in reality, a program runs on the main memory under the control of the O8, and data is frequently written to most areas of the main memory, and there are only a few areas where only data is read. Therefore, reading, writing, and patrolling the entire main memory causes great waste in terms of minimizing the amount of hardware that operates in order to maintain the reliability and usefulness of the computer.

(4) Purpose of the Invention The present invention has been made by focusing on the above-mentioned conventional problems, and its purpose is to provide a method that can detect and correct errors in main memory with simple operations. This aims to shorten the time required for main memory patrol and improve the reliability and usefulness of computers.

(5) Structure of the Invention In order to achieve the above object, the present invention connects an error address register between an address register and a patrol control section, and connects an error address register between an imposition detection correction section and a patrol control section. A 1-bit error flag is connected, and a 1-bit error discovered when the CPU performs arithmetic processing and its address are held in the 1-bit error 7 lag and error address register, and these 1-bit error flags and their addresses are stored during main memory patrol. A main memory patrol method detects the presence or absence of a 1-bit error in main memory by searching an error address register, and if there is a 1-bit error, the error is corrected and rewritten to main memory. The purpose is to realize the following. below,
Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(6) Embodiment of the Invention FIG. 3 is a diagram showing an embodiment of the block configuration of main memory patrol to which the present invention is applied. As is clear from this figure, in the SOU 2, there is a 1-bit error flag 5 connected to the error detection and correction section 23, and an error address register 26 connected to the address register 21.
are built in, and output to the patrol control unit 12 built into the CPU i. and,
The patrol control section 12 is connected to the MSU 3 via the address register 21 and the error address register, or the error detection and correction section n and the 1-bit error 7 lag 25 port. The 1-bit error flag b is normally in an OFF state, and is turned on when the error detection and correction unit n detects a 1-bit error when data is read during arithmetic processing by the CPU 1. In addition to notifying the existence of a bit error, the above ff
1 It is reset after the patrol ends. Further, the error address register 26 is used to hold the address where the error occurs when the 1-bit error is detected. Note that the other configurations within the SOU 2 and the configurations of the CPU 1 and MSU 3 are the same as in the above-mentioned conventional system.

In such a configuration, when performing normal arithmetic processing, memory access is performed from O8 etc. and data at a predetermined address A is read out, as in the above-mentioned conventional case. If there is a 1-bit error during this read access, the error detection and correction unit n detects the error bit A of the address A.
It is corrected and sent to the CPU 1, where arithmetic processing is performed, while the 1-bit error detection signal is sent to the 1-bit error 7lag b and turned on, and the address A at that time is copied to the error address register 26. put. Note that in this arithmetic processing, the corresponding address A in MSU3 is not corrected.

Next, when performing main memory patrol, first the timer 13
is activated and outputs an interrupt signal. This timer 13 operates at predetermined time intervals and outputs an interrupt signal each time, and the interrupt signal causes O8 to interrupt normal arithmetic processing and activates the patrol control section 12. This patrol control unit 12 searches for 1-bit error 7 lag 3, and if the 1-bit error flag 25 is off, it ends the main memory patrol, sends a completion report to O8, and O8 is interrupted. Resume the arithmetic processing that was being performed.

On the other hand, in the above main memory patrol, when the 1-bit error flag b is on, the address A stored in the error address register 26 is read, the 1-bit error flag is reset for 25 minutes, and the data is read via the memory access unit 11ft. Register that address and access it. The read data undergoes error correction in the error detection and correction section n, is written again to the same address of the MSU 3, and is then reread from this address A. Here, the patrol control unit 12 once again searches for the 1-bit error 7 lag δ, and if the 1-bit error 7 lag b is off, it ends the main memory patrol. That is,
The fact that the 1-bit error flags were turned off by the second search means that the soft error was corrected by rewriting the data.

However, if the 1-bit error 7lag b is turned on again in the second search, a fixed fault (8-dead error) will occur at this address A. in this case,
Check whether there is a burst error in the main memory, that is, error bit A of address A, and other addresses at the same bit position (
It is also checked whether there is an error in the bits (indicated by B in FIG. 2, for example) (B, in the same figure). This check is performed by successively accessing other bits B of the same memory chip that include the memory cell corresponding to the error bit AI, and checking whether 1-bit error 7 lag 3 is turned on in this case. conduct. During this check operation, if several other bits are checked and no error has occurred, this indicates that it is not a burst error, and the main memory patrol is then terminated.

Unlike the above, if an error occurs when checking several other bits of the same memory chip, it is regarded as a burst error and this memory chip is replaced with a replacement chip. The replacement chip is juxtaposed to the data bit and the EOO bit, as shown by S in FIG.
Normally, data is not written, but when a burst error is corrected, data is written in place of the chip in which the error occurred. Note that even in the case of the above-mentioned 1-bit error, ie, a soft error, it is possible to correct the error by replacing the chip with a replacement chip, but this is not preferable because the replacement chip would be wasted. In other words, replacing the chip with a 1-bit error is effective in preventing another bit error from occurring in the same data, resulting in a 2-bit error, making it impossible to correct the error, but replacing the chip with the same data Since the probability that 2 bits will become an error in a chip (consisting of several tens of bits) is very small, there is no need to replace chips especially for a 1-bit error. On the other hand, in the case of a burst error, the entire series of memory chips (several kilograms and hundreds of kilograms) is in error, so the probability of one more bit error occurring in one of the words cannot be ignored. It disappears. Therefore, it is effective to correct the error by replacing the memory chip only once a burst error occurs, in order to maintain the reliability and usefulness of the combiator. The memory chip that caused the burst error can be identified from the error bit position and address in each word, and the error pin is detected.A1. B, the position is detected by the error detection and correction unit n.

As described in detail, according to the present invention, a 1-bit error flag and an error address register that holds this 1-bit error address are connected to the main memory, and a 21-bit error is detected during arithmetic processing. Keep it in the above register,
During main memory patrol, which is carried out periodically, the CPU
By searching the bit error flag and error address register, the presence or absence of an error is detected, and soft errors and burst errors are corrected. Various effects can be produced, such as being able to complete the patrol in a short time and increasing the normal calculation processing time of the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional computer equipped with a main memory patrol function, FIG. 2 is a diagram showing a model of the data storage system in the main memory, and FIG. This is a configuration diagram of a computer for practicing the memory roll method. 1...CPU 2...5OU3...
MSU 11...Memory access unit 12
...Patrol control unit 13...Timer 21...
Address register 22...Check bit generation section n
...Error detection and correction unit 24...Chip replacement control unit 3
...1-bit error flag 26...Error address register 'glossy part' Fig. 1 Fig. 2

Claims (1)

[Claims] A 1-bit error 7 lag is connected between the patrol control unit and the error detection/correction unit, while an error address register is connected between the patrol control unit and the address register, and the central processing unit performs normal main memory access. The 1-bit error and its address found at the time of execution are retained in the 1-bit error flag and error address register mentioned above, and by searching these 1-bit error flag and error address register during main memory patrol, the 1-bit error and its address are stored in the main memory. Is there a 1-bit error, and if so, what is the address? 1. A main memory patrol method characterized in that when a 1-bit error is detected, the error is corrected and then written to the main memory again to correct the error.