JPS63187500A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the increase in the period of patrol by arranging the function of the patrol decentralizingly to a semiconductor storage device. CONSTITUTION:A gate array having several thousands of -several tens of thousands of gates is manufactured recently comparatively easily and it is possible to decentralize the function to each semiconductor storage device 1. The patrol function is provided decentralizing by N-set of semiconductor storage device 1 and patrol is applied to each decentralized unit. Thus, it is not required to apply patrol of memory on by one word via a memory bus 3, then the execution of the main program is not hindered by the patrol program and when the capacity of the memory is increased, the increase in the patrol period with respect to one address is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device built into an information processing device, which particularly requires a large storage capacity and high reliability. The present invention relates to a semiconductor memory device suitable for use in an information processing device.

[Conventional technology]

It is known that when a semiconductor memory element is used in a memory circuit, data errors occur at a certain rate due to the influence of alpha rays and the like. In particular, information processing devices that require large-capacity storage circuits may use as many as 1,000 or more semiconductor storage elements, which is a factor that limits the reliability of the device. Therefore, conventionally, it is common to have an error correction circuit that corrects even if a 1-bit error occurs in one word read from a semiconductor memory circuit.

When high reliability is required for semiconductor storage devices, 1
One possible method is to perform preventive maintenance based on the number of bit errors that occur. This can be achieved, for example, by providing a counter for counting the occurrence of 1-bit errors in the storage device, and having the CPU periodically read out the counter, as seen in Japanese Patent Laid-Open No. 61-11854.

Still another method is to start a patrol program separate from the user program at regular intervals in order to reduce the probability that an uncorrectable error of 2 bits or more will occur. patrol program.

The contents of a semiconductor memory device are sequentially read, and if there is a 1-bit error, it is corrected and rewritten.

[Problems to be Solved by the Invention] The conventional system described above has a problem in that when the capacity of a semiconductor storage device increases dramatically, the frequency of patrols decreases significantly. It is expected that the capacity of semiconductor storage devices will increase by 16 times its current level in 2-3 years based on the current rate of increase. The frequency of patrolling one word in the storage device will be reduced to one-sixteenth of the current frequency.

Although it is possible to improve the patrol frequency by shortening the activation period of the patrol program, in this case, the execution speed of the main program will be reduced, and the period cannot be shortened unnecessarily.

In order to alleviate this problem, for example,
As shown in 96, it is conceivable to implement the patrol function in hardware and perform patrol continuously instead of at predetermined intervals while there is no access from the CPU. However, in this method, the patrol hardware needs to know that the CPU will not access the memory, and a special communication signal is required.

[Means for solving problems]

The above problem is caused by centrally managing patrol via a memory bus, and can be solved by distributing the patrol function to the semiconductor storage device.

In the past, it was necessary to limit the functionality of semiconductor memory devices as much as possible to reduce hardware costs, but now gate arrays with several thousand or more gates can be manufactured relatively easily. As described in , it has become possible to distribute functions to each semiconductor memory device.

[Effect]

By having the patrol function distributed among N semiconductor storage devices, it is possible to perform patrols simultaneously for each distributed unit, so the interval at which one word of the storage device is patrolled from one word to another can be centrally controlled. In the same case as in the case of , when focusing on a certain word, the frequency with which that word is patrol accessed increases by an amount multiplied by N compared to the case of centralized management.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a semiconductor memory device according to the present invention. 1 represents a semiconductor memory device mounted on a printed wiring board, and 3 represents a data processing device (CPU, not shown).
), 10 to 14 are internal circuits of the semiconductor storage device, and 10 is the memory bus 3.
20 is a patrol circuit; 30 is a memory bus interface circuit that gives priority to access from the CPU when memory access from the CPU and access from the patrol circuit 20 occur simultaneously; A priority determination control circuit performs access, and 40 is a storage circuit for storing data. 2
The patrol circuit shown at 0 periodically reads the memory circuit 40 and stores 1 bit (bit) as described below.
) If an error is detected, the data is corrected and written to the same address.

FIG. 2 is a diagram showing the connection relationship between the CPU 2 and the semiconductor memory device 1. This figure shows an example in which four semiconductor memory devices 1 are connected to one CPU 2 via the memory bus 3. One semiconductor memory device 1 detects that it is selected by some of the address signals in the memory bus 3 and exchanges data with the CPU 2 .

FIG. 3 is a diagram showing the detailed configuration of the semiconductor memory device explained in FIG. 1.

11 to 14 are interface circuits 10 with the memory bus
, 11 is a register (RDT) that holds data read from the memory circuit 40, 12 is a register (WDT) that holds data to be written to the memory circuit 40, and 13 is a register (that holds the address for executing the above operation). A
DR), and 14 represents a control signal interface circuit (CTL). 21 to 28 are elements constituting a patrol circuit. 21 is a circuit that generates a periodic signal for patrolling. In this embodiment, a constant periodic signal is generated inside the semiconductor storage device, but the period can be made variable by providing a control signal on the memory bus. too,
It is also possible to create patrol timing by providing a periodic signal directly on the memory bus. 22 is a circuit that controls the patrol operation, 23 is a counter (ACNT) that generates the address to be patrolled, 24 is a register (APR) that holds the address where a reading error has occurred, and 25 is a circuit that controls the patrol operation. A register (S) that holds information about the bit position where an error occurred
DR). 26 is a circuit for detecting and correcting data errors (ECCCK-CR), 27 is a register (RBF) that holds the corrected data, and 28 is a circuit that generates a correction code for error correction (ECCGN). It is.

Reference numeral 30 is a circuit that determines the priority of access to the memory circuit 40 (hereinafter abbreviated as the memory circuit) and also controls the memory. In this embodiment, a dynamic RAM is used as the memory circuit 40. , the priority is the order of refresh, memory access from the CPU, and patrol access. Note that if a static RAM is used as the memory circuit 40, the refresh circuit 44 is not necessary.

41 to 44 are examples of configuring the memory circuit 40;
represents a semiconductor memory element, 42 represents a write data buffer (WBF), and 43 represents an address buffer (ABF).These are for distributing each signal to a large number of memory elements. 44 is a circuit for refreshing the dynamic RAM.

In FIG. 3, when a data read request is issued from the CPU 2, priority determination is performed by the priority determination control circuit 30 through 14 interface circuits, and if there is no refresh request, data is read from the memory element 41 and an error is detected. -Hold in the read data register 11 through the correction circuit 26. At this time, the address is transmitted to the memory element 41 through the address register 13 and address buffer 43.

On the other hand, the control circuit 22 issues a patrol request every fixed period generated by the timer circuit 21.

If there is no access from the refresh circuit 44 or the CPU 2 at the same time, this patrol request is accepted by the priority determination control circuit 30, and the data at the address indicated by the address counter 23 is read.

The read result is transmitted from the error detection/correction circuit 26 to the control circuit 22, and if there is no error, the patrol request is canceled and a pulse is output to the address counter 23 to cause it to count up. If the read result is a 1-bit error, the corrected data is temporarily held in the data register 27, an error correction code is added by the circuit 28, and after writing to the memory element 41, the address counter is incremented. conduct. At this time, the control circuit 2
2. Leave the request open. If a reading error occurs, the address is held in the address freeze register 24, and information on which bit position the error occurred is held in the syndrome register 25. Although it is possible to display this information by providing a lamp on the semiconductor memory device 1, in this embodiment, the outputs of the address freeze register 24 and the syndrome register 25 are both read data registers so that they can be read by the CPU. 11 input.

If an error of 2 bits or more occurs, the error detection/correction circuit 26 cannot correct the data, so the control circuit 22 performs the same operation as when the data is read correctly. Therefore, the above-mentioned error of 2 bits or more is reported to the system program only when the CPU performs a read access to that address.

〔Effect of the invention〕

According to the present invention, there is no need to patrol the memory word by word via the memory path, so the execution of the main program is not hindered by the patrol program, and even when the memory capacity increases,
It is possible to prevent an increase in the patrol cycle for addresses. Further, the entire circuit can be housed in one gate array LSI, and there is no practical problem in increasing the quantity and cost due to the adoption of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the invention, FIG. 2 is a diagram showing the positioning of the invention in an information processing apparatus, and FIG. 3 is a diagram showing the detailed configuration of the invention. 1... Semiconductor storage device, 2... CPU, 10...
Memory path interface, 20...Patrol circuit, 1st day rate 2 figures and 3 figures

Claims (1)

[Claims] 1. A patrol circuit that periodically performs read access to a memory circuit that stores data, and if a 1-bit error is detected in the read data, corrects the data and returns it to the same address. In a semiconductor memory device having error detection/correction and rewriting functions for performing a write operation,
A priority determination control circuit that gives priority to the access from the data processing device and accesses the storage circuit when there is an access from the data processing device and an access from the patrol circuit at the same time; Therefore, when a 1-bit error is detected, a means is provided to continue the access request from the patrol circuit during the period from error detection to the end of writing of correction data. A semiconductor memory device characterized in that a memory access request from the processing device is blocked. 2. The scope of claims characterized in that the memory address is updated by the patrol circuit on the condition that there is no error in the read data, or if there is an error, the corrected data is written. 2. The semiconductor memory device according to item 1.