JPS5856195B2 - Diagnostic method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for diagnosing a semiconductor memory device used in an electronic computer, and particularly to an online diagnosis.

Conventional online diagnostic methods for storage devices include when the storage device is idle, that is, when the central processing unit (CPU) is not using the storage device, or when the CPU is not using the storage device in a storage device that uses a dynamic storage element. A method has been used in which a diagnostic device accesses the storage device, reads it out, and checks it when the storage device is not running and no refresh operation is being performed (a typical checking method is a parity check).

Another method is to use multi-programming technology to run various diagnostic programs such as a storage device diagnostic program in a time-sharing manner with the original program without having to purchase a special diagnostic device.

In any case, the scale of the hardware and software is large and the economic cost is high.

This invention (in this case, in a dynamic storage device, by simply adding very simple hardware, refresh operation and storage device diagnosis can be performed simultaneously, that is, in the same cycle, making it extremely easy to perform online diagnosis). It can be carried out.

Before presenting an embodiment, the operation of a dynamic memory will be briefly described.

A dynamic memory element is one that uses a capacitor as a memory element, and the presence or absence of a charge is used as information.
It corresponds to nQ97.

Normally, this charge gradually disappears due to leakage resistance in the circuit, so to prevent this, it is necessary to reinforce the charge at regular intervals.

This is called refresh.

The method of refreshing will be explained using diagrams.

In FIG. 1, 100 is a CPU, 101 is a timing control circuit, and 102 is a memory device, including memory elements and buffers (
(not shown here).

In normal operation, the CPU 100 sends a memo IJ IJ quest signal 103 and address signals 104-1 and 104.
-1, a signal 105 indicating either reading or writing, and if signal 105 indicates a write instruction, write data 106 is output.

A signal 107 is a read signal from the memory, and a signal 108 is a parity error signal.

A timing control circuit 101 receives a memory request signal, etc., and a timing generator 109 sends out pulses 110 and 111 (not directly related to this invention and omitted) necessary for the memory.

Write data 106 is buffered by buffer gate 111 and sent to memory.

A parity generator 112 is usually added and the parity bits are also sent to memory.

Memory read signal 113 is sent to CPU 100 via buffer gate 114.

Signal 115 is a pari bit read signal, and signal 113
At the same time, the parity checker 116 # outputs an error signal 108 if there is a parity error.

The address signal is related to the refresh operation and is particularly important in this invention, so it will be described in detail below.

Assuming that the memory device 102 uses 4 memory elements (more specifically, 4096 words), the signal 104-1 is the LSB (LeastSlgn) of the address signals.
A in order from ificant Bit).

, A1. A2゜A3. A4. A5 is assigned, and signal 104-2 is assigned the most MSB (Most 51gn1fi
cant Bit) towards A6. A7. A8. A9.
Alo and A11 are assigned.

Ao corresponds to 2°f and A11 corresponds to 211 rl. In other words, A.

is the LSB, and A1 is the MSB. During normal operation, i.e., not refreshing, signal 117 is connected to multiplexer 1.
18 selects the address signal 10.11-1, the address signal 104-1 itself is output.

During the refresh cycle, MPX118 uses counter 11.
Since the signal 120 of 9 is selected, the signal 117 is the signal 120.
becomes the same as

The refresh operation will be explained using FIG.

In Figure 1, 121-1 and 121-2 are already MAR (Me
address register),
122 is a memory element.

(As mentioned above, the memory element in tc4 is 4096 words,
Although it is a 1-bit element, the inside of the memory is a matrix cell with 64×64 rows and columns.

In other words, an arbitrary address is represented by an intersection of m and n lines.

This is expressed as (m, n).

When (m, n) is selected and a memory request signal 108 is received, the memory cells on row m (64 cells in total) are first selected, and the presence or absence of charge is checked regardless of whether the read or write instruction 105 is issued. .

After knowing the presence or absence of a charge, if that cycle was a read instruction, rewriting the charge completely will simultaneously determine the presence or absence of a charge in the cell at the intersection of the 1st row, digit, m1, column n. output pin to the output pin.

This charge rewriting is automatically performed within the device.

On the other hand, if it is a write instruction, a charge corresponding to write data t is newly written only to the cell on row m and column n, but the previously read data, ie, charge, is rewritten to the other 63 cells.

The refresh cycle period is determined as follows.

Normally, the refresh period of a memory device is 2m5 (2xi
o' seconds).

As mentioned earlier, one row can be refreshed all at once, so starting from row O, refresh 1/ts is performed one after another.

Therefore, there are 64 lines in memory at address 4096, so
The refresh interval is 2mS/64:32μs (32X
10-seconds).

In other words, a refresh cycle is issued from the timing generator 109 at 32 μs, and at the same time (this counter 119 also
Count up one by one.

Note that refresh takes priority over CPU access.

Furthermore, since the purpose of refresh is usually just to rewrite the charge, the contents of the address register 121-2 may be anything during this operation, and are not particularly controlled.

Cell information of the intersection of the currently selected row m' and any column n' is output from the memory element, but since it is unnecessary for the CPU 100, the timing control circuit 101 controls so that this signal is not output.

(not shown here). As is clear from the above explanation, there is essentially no difference between a refresh cycle and a read cycle from the perspective of a memory device.

The only difference is that it does not send data to the CPU, and that it ignores column addresses.

Diagnose the memory in a system configured as shown in Figure 1 (this is done by multi-programming, and in addition to the user's program (this diagnostic program is resident in one memory), Diagnose memory by detecting when the user is not using it.

Since this method requires the diagnostic program itself to be stored in memory, it is impossible to diagnose if any part of the program is malfunctioning.

Also, although multiprogramming is possible on large computers, medium and small computers do not have this function, so diagnosis is inevitably a one-off offline diagnosis, which is inefficient.

On the other hand, there is also a method of diagnosing using hardware without using software.

For example, in addition to the above-mentioned timing control circuit, there is a method in which a dedicated diagnostic device is provided to check whether the CPU is not in use or not in a refresh cycle, access the memory, and check parity.

However, this requires hardware that is at least as large as the timing control circuit, leading to an increase in cost.

Furthermore, another drawback is that even if you try to perform an actual memory cycle immediately after the diagnostic cycle has started, you will not be able to access the memory until the diagnostic cycle ends, which will have a big impact on the system.

This invention aims to eliminate these drawbacks.

This will be explained with reference to FIG. In FIG. 2, the same numbers as in FIG. 1 indicate the same signals or devices.

The basic difference between FIG. 2a and FIG. 1a is that an address multiplexer (MPX) 218 and an address counter 219 are added.

That is, the counter 219 is a 6-bit counter that counts up in response to the carry signal 230 of the refresh address counter 119.

This becomes the column address to memory at refresh time.

That is, in a normal cycle, MPXl, 18 and 21
8 is the address 104=1 and 104- of the CPU 100
2 is selected, but the outputs 120 and 22 of the refresh address counters 119 and 219 during refresh are selected.
Select 0 and send to memory.

To aid in understanding the invention, a detailed diagram of the address signal system is shown in FIG.

As shown in FIG. 2, the counters 119 and 219 are initially reset, and when the first refresh cycle begins, the MPXs 118 and 218 select the address signals of the refresh counters 119 and 219. At the same time, the column address is 0, so the memory address (
0°O) is read out.

After a further certain period of time (as mentioned above (approximately 32 μs)), the refresh cycle starts again.

At this time, since the row counter has been incremented by 1, row 1 of the memory is selected and refreshed.

- Since the blade row address has not yet received the carry signal 230 from the counter 119, it remains in its previous state, that is, O.

Therefore, at this time, the contents of address (1, O) are read out.

Similarly, every refresh cycle, the counter 11
9 counts up to the highest (111111).

That is, row 63 is selected. Until this time, the column counter 219 remains at (oooooo) and column O is selected.

After refreshing row 63 and reading memory address (63,0), row counter 119 is (000000))
At this time, a carry signal 230 is generated and the column counter 219 counts up by +1.

Therefore, in the next refresh cycle, row O is refreshed all at once, and at the same time the contents of address (oti) are read out.

Thereafter, the address of the memory advances by one in each refresh cycle, and when it reaches the end (63, 63), it returns to (0, 0) iv again.

In this way, all memory addresses are read at the same time as refresh (this happens), so if you check the memory parity each time, you will have diagnosed the entire memory area.

Of course, at this time, since the read data is not necessary for the CPU 100 (data that would normally cause trouble even if sent to the CPU 100 is blocked by the timing control circuit 201 (not shown here), the parity error signal Only 108 sends CPUI 00s.

When the CPU 100 receives the parity error signal 108, it knows that there is an error in the memory and may stop the operation immediately, or it may use some kind of error analysis routine, for example, to sequentially read all memory addresses. The CPU 100 accesses this address and checks the address where the error occurred, or, although not shown here, the CPU 100 accesses the timing control circuit 20.
The contents of the row and column counters 119 and 219 of 1 may be directly read to find out where the error address was.

The former error analysis routine does not detect intermittent errors (instantaneous failures 9).

In other words, since an error is detected during refresh diagnostics, the memory is immediately read sequentially starting from address O.However, in the case of an intermittent error, even if it is read later, it is no longer a failure, so it is not detected as an error. It is not possible to know the error address, and only information that there was an error during refresh is obtained.

However, in the latter analysis routine, the values of the row and column address counters 119 and 219 are sent directly to the CPU 100.
is read out, so you can see the first gill location directly.

Therefore, when reading that address again, if there is an error, it is a fixed failure, and if the error does not occur, it is known that it was an intermittent error, which is useful for preventing failures.

As explained above, according to the present invention 1, in a dynamic IC memory device 1, all memory areas can be sequentially diagnosed online at the same time as refreshing by simply adding some hardware to the conventional timing control circuit. Can diagnose faults in memory and even computer systems,
This is extremely useful for preventive maintenance.

[Brief explanation of the drawing]

Fig. 1a is a block diagram of a memory system using a conventional dynamic type IC memory, Fig. 1 is a detailed diagram of the address system of Fig. 1a, and Fig. 2a is an embodiment of the dynamic type A block diagram of the IC memory system, Figure 2 is a detailed diagram of the address system in Figure 2a, and 100 is a CP
U, 101 is a memory device, 218 is an address multiplexer, and 219 is an address counter. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Claims] 1. A diagnostic method for a semiconductor memory device using a dynamic semiconductor memory element (herein, a diagnostic method characterized by refreshing and diagnosing the memory device within a refresh cycle).