JPS5698781A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5698781A
JPS5698781A JP17349479A JP17349479A JPS5698781A JP S5698781 A JPS5698781 A JP S5698781A JP 17349479 A JP17349479 A JP 17349479A JP 17349479 A JP17349479 A JP 17349479A JP S5698781 A JPS5698781 A JP S5698781A
Authority
JP
Japan
Prior art keywords
data
address
memory
corrected
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17349479A
Other languages
Japanese (ja)
Inventor
Yoshifumi Sasamoto
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP17349479A priority Critical patent/JPS5698781A/en
Publication of JPS5698781A publication Critical patent/JPS5698781A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Abstract

PURPOSE:To prevent the accumulation of errors of data read out in a rare case by readling all data out of memory cells within a definite time during refreshing operation, and by correcting and rewriting erroneous data in a memory if it is detected. CONSTITUTION:In refreshing operation, a refresh address generating circuit (composed of refresh counter 23 and refresh address register 24) generates cyclically a column address for selecting readout data bits and a chip selection address and, while reading all memory contents of memory part 21, detects 28 an error of the readout data; erroneous data is corrected 31 and the corrected data and a check bit are rewritten together in the address where the error occured. Therefore, even an error of data read out of an address read out in a rare case is corrected and the accumulation of errors is prevented.
JP17349479A 1979-12-29 1979-12-29 Semiconductor memory device Pending JPS5698781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17349479A JPS5698781A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17349479A JPS5698781A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5698781A true JPS5698781A (en) 1981-08-08

Family

ID=15961542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17349479A Pending JPS5698781A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5698781A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4465101A (en) * 1981-09-29 1984-08-14 Toyota Jidosha Kabushiki Kaisha Changeover valve unit for power-assisted steering systems
JPS62185296A (en) * 1986-02-10 1987-08-13 Nec Corp Memory device
JPH0713786A (en) * 1992-11-30 1995-01-17 Internatl Business Mach Corp <Ibm> Method and apparatus for correciton of error
US7017027B2 (en) 2002-09-26 2006-03-21 Elpida Memory, Inc. Address counter control system with path switching
JP2007087435A (en) * 2005-09-16 2007-04-05 Toshiba Corp Semiconductor storage device
JP2014502771A (en) * 2010-12-10 2014-02-03 クアルコム,インコーポレイテッド Embedded DRAM with low power self-correction capability
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127036A (en) * 1976-04-16 1977-10-25 Mitsubishi Electric Corp Diagnostic system
JPS52129334A (en) * 1976-04-23 1977-10-29 Nec Corp Memor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127036A (en) * 1976-04-16 1977-10-25 Mitsubishi Electric Corp Diagnostic system
JPS52129334A (en) * 1976-04-23 1977-10-29 Nec Corp Memor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4465101A (en) * 1981-09-29 1984-08-14 Toyota Jidosha Kabushiki Kaisha Changeover valve unit for power-assisted steering systems
JPS62185296A (en) * 1986-02-10 1987-08-13 Nec Corp Memory device
JPH0713786A (en) * 1992-11-30 1995-01-17 Internatl Business Mach Corp <Ibm> Method and apparatus for correciton of error
US7017027B2 (en) 2002-09-26 2006-03-21 Elpida Memory, Inc. Address counter control system with path switching
JP2007087435A (en) * 2005-09-16 2007-04-05 Toshiba Corp Semiconductor storage device
JP2014502771A (en) * 2010-12-10 2014-02-03 クアルコム,インコーポレイテッド Embedded DRAM with low power self-correction capability
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh

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