JPS5798197A - Multiplexing memory device - Google Patents
Multiplexing memory deviceInfo
- Publication number
- JPS5798197A JPS5798197A JP55173754A JP17375480A JPS5798197A JP S5798197 A JPS5798197 A JP S5798197A JP 55173754 A JP55173754 A JP 55173754A JP 17375480 A JP17375480 A JP 17375480A JP S5798197 A JPS5798197 A JP S5798197A
- Authority
- JP
- Japan
- Prior art keywords
- read
- out data
- memory
- addresses
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Abstract
PURPOSE:To output a correct read-out data of all addresses, in case when addresses having a faulty bit of each memory are different from each other, by selecting one of read-out data from plural memories by an error output signal of a checking circuit. CONSTITUTION:This device has memories MEMI, MEMZ, and writes the same data simultaneously in each memory when writing, and selects and outputs one of read-out data of each memory by a selecting circuit when reading out. In this case, an error of each read-out data is checked by a checking circuit 4, and one of read-out data is selected by the selecting circuit 1 in accordance with an error output signal S, therefore, even if each memory has a faulty bit, a correct read-out data is outputted relating to all addresses having a read-out request, in case when addresses having a faulty bit are different from each other in each memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173754A JPS5798197A (en) | 1980-12-11 | 1980-12-11 | Multiplexing memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173754A JPS5798197A (en) | 1980-12-11 | 1980-12-11 | Multiplexing memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5798197A true JPS5798197A (en) | 1982-06-18 |
Family
ID=15966509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55173754A Pending JPS5798197A (en) | 1980-12-11 | 1980-12-11 | Multiplexing memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5798197A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5990150A (en) * | 1982-11-15 | 1984-05-24 | Meidensha Electric Mfg Co Ltd | Double structure method of input and output device |
EP1634172A2 (en) * | 2003-06-02 | 2006-03-15 | Atmel Corporation | Fault tolerant data storage circuit |
-
1980
- 1980-12-11 JP JP55173754A patent/JPS5798197A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5990150A (en) * | 1982-11-15 | 1984-05-24 | Meidensha Electric Mfg Co Ltd | Double structure method of input and output device |
JPH0139134B2 (en) * | 1982-11-15 | 1989-08-18 | Meidensha Electric Mfg Co Ltd | |
EP1634172A2 (en) * | 2003-06-02 | 2006-03-15 | Atmel Corporation | Fault tolerant data storage circuit |
EP1634172A4 (en) * | 2003-06-02 | 2006-08-30 | Atmel Corp | Fault tolerant data storage circuit |
US7181650B2 (en) | 2003-06-02 | 2007-02-20 | Atmel Corporation | Fault tolerant data storage circuit |
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