JPS5798197A - Multiplexing memory device - Google Patents

Multiplexing memory device

Info

Publication number
JPS5798197A
JPS5798197A JP55173754A JP17375480A JPS5798197A JP S5798197 A JPS5798197 A JP S5798197A JP 55173754 A JP55173754 A JP 55173754A JP 17375480 A JP17375480 A JP 17375480A JP S5798197 A JPS5798197 A JP S5798197A
Authority
JP
Japan
Prior art keywords
data
read
memory
addresses
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173754A
Other languages
Japanese (ja)
Inventor
Tsune Morioka
Moriyuki Takamura
Yukio Nozoe
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55173754A priority Critical patent/JPS5798197A/en
Publication of JPS5798197A publication Critical patent/JPS5798197A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/74Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Abstract

PURPOSE:To output a correct read-out data of all addresses, in case when addresses having a faulty bit of each memory are different from each other, by selecting one of read-out data from plural memories by an error output signal of a checking circuit. CONSTITUTION:This device has memories MEMI, MEMZ, and writes the same data simultaneously in each memory when writing, and selects and outputs one of read-out data of each memory by a selecting circuit when reading out. In this case, an error of each read-out data is checked by a checking circuit 4, and one of read-out data is selected by the selecting circuit 1 in accordance with an error output signal S, therefore, even if each memory has a faulty bit, a correct read-out data is outputted relating to all addresses having a read-out request, in case when addresses having a faulty bit are different from each other in each memory.
JP55173754A 1980-12-11 1980-12-11 Multiplexing memory device Pending JPS5798197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173754A JPS5798197A (en) 1980-12-11 1980-12-11 Multiplexing memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173754A JPS5798197A (en) 1980-12-11 1980-12-11 Multiplexing memory device

Publications (1)

Publication Number Publication Date
JPS5798197A true JPS5798197A (en) 1982-06-18

Family

ID=15966509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173754A Pending JPS5798197A (en) 1980-12-11 1980-12-11 Multiplexing memory device

Country Status (1)

Country Link
JP (1) JPS5798197A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990150A (en) * 1982-11-15 1984-05-24 Meidensha Electric Mfg Co Ltd Double structure method of input and output device
EP1634172A2 (en) * 2003-06-02 2006-03-15 Atmel Corporation Fault tolerant data storage circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990150A (en) * 1982-11-15 1984-05-24 Meidensha Electric Mfg Co Ltd Double structure method of input and output device
JPH0139134B2 (en) * 1982-11-15 1989-08-18 Meidensha Electric Mfg Co Ltd
EP1634172A2 (en) * 2003-06-02 2006-03-15 Atmel Corporation Fault tolerant data storage circuit
EP1634172A4 (en) * 2003-06-02 2006-08-30 Atmel Corp Fault tolerant data storage circuit
US7181650B2 (en) 2003-06-02 2007-02-20 Atmel Corporation Fault tolerant data storage circuit

Similar Documents

Publication Publication Date Title
DE3587145T2 (en) BUFFER SYSTEM WITH DETECTION OF READ OR WRITE CIRCUIT ERRORS.
JPH02166700A (en) Nonvolatile semiconductor memory device with built-in error inspecting and correcting device
FR2374690B1 (en)
JPS57117198A (en) Memory system with parity
JPS5798197A (en) Multiplexing memory device
JPS58128077A (en) Memory device
JPS598198A (en) Memory bit error monitor device
JPS63753A (en) Test system for memory error checking and correcting circuit
JPS5637899A (en) Memory malfunction detection system
JPS6247900A (en) Memory device
JPS5736500A (en) Memory check system
JPS5727342A (en) Error checking system for error detecting correcting circuit
JPS5782298A (en) Diagnostic system for storage device
JPS5733497A (en) Memory testing system
JPS6432500A (en) Semiconductor storage device
JPS58194200A (en) Memory control circuit
JPH01177146A (en) Memory checking circuit
JPS60186951A (en) Memory check system
JPS56165997A (en) Parity check system for storage device
JPS5478036A (en) Control system of multiplexing memory unit
JPS57109198A (en) Error processing system
JPS58115699A (en) Memory board test system
JPS57109199A (en) Alternate memory check system
JPS6083160A (en) Data processor
JPS6134648A (en) Storage device