JPS5698780A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5698780A
JPS5698780A JP17349379A JP17349379A JPS5698780A JP S5698780 A JPS5698780 A JP S5698780A JP 17349379 A JP17349379 A JP 17349379A JP 17349379 A JP17349379 A JP 17349379A JP S5698780 A JPS5698780 A JP S5698780A
Authority
JP
Japan
Prior art keywords
error
memory
data
memory cells
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17349379A
Other languages
Japanese (ja)
Inventor
Yoshio Nakano
Yoshifumi Sasamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17349379A priority Critical patent/JPS5698780A/en
Publication of JPS5698780A publication Critical patent/JPS5698780A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the accumulation of a data error stored in a readout address by detecting the error by reading all data out of memory cells within a definite time during refreshing operation.
CONSTITUTION: A refresh address generating circuit generates cyclically both a refresh address (row address) required for refreshing and a column address selecting a readout data bit to read all memory cells within a definite time. In the refreshing of memory 21, the said refresh address generating circuit reads all data out of the memory cells and provides error detection 28 of the readout data, and if an error is detected, it is displayed in a memory device by error display circuit 29. In case of random memory destruction due to (α) rays, etc., the accumulation of the error is prevented, and the reliability is improved.
COPYRIGHT: (C)1981,JPO&Japio
JP17349379A 1979-12-29 1979-12-29 Semiconductor memory device Pending JPS5698780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17349379A JPS5698780A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17349379A JPS5698780A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5698780A true JPS5698780A (en) 1981-08-08

Family

ID=15961523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17349379A Pending JPS5698780A (en) 1979-12-29 1979-12-29 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5698780A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242396A (en) * 1985-08-15 1987-02-24 マイテル・コ−ポレ−シヨン Dynamic memory refresh and parity checking circuit
JP2014502771A (en) * 2010-12-10 2014-02-03 クアルコム，インコーポレイテッド Embedded DRAM with low power self-correction capability
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127036A (en) * 1976-04-16 1977-10-25 Mitsubishi Electric Corp Diagnostic system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127036A (en) * 1976-04-16 1977-10-25 Mitsubishi Electric Corp Diagnostic system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242396A (en) * 1985-08-15 1987-02-24 マイテル・コ−ポレ−シヨン Dynamic memory refresh and parity checking circuit
JP2014502771A (en) * 2010-12-10 2014-02-03 クアルコム，インコーポレイテッド Embedded DRAM with low power self-correction capability
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh

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