JPS5677985A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5677985A
JPS5677985A JP15276679A JP15276679A JPS5677985A JP S5677985 A JPS5677985 A JP S5677985A JP 15276679 A JP15276679 A JP 15276679A JP 15276679 A JP15276679 A JP 15276679A JP S5677985 A JPS5677985 A JP S5677985A
Authority
JP
Japan
Prior art keywords
data
error
refresh cycle
during
specified address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15276679A
Other languages
Japanese (ja)
Inventor
Ginzo Yamazaki
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP15276679A priority Critical patent/JPS5677985A/en
Publication of JPS5677985A publication Critical patent/JPS5677985A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Abstract

PURPOSE:To increase both reliability and data processing capacity, by reading the data of the specified address during a refresh cycle and then carrying out the detection and correction of an error of the read-out data. CONSTITUTION:The column address strobe (CRAS) signal or the chip selection signal is applied selectively to the specified block within the memory element blocks 1A1-1An and 1D1-1Dn during the refresh cycle. Then the data of the specified address is read out to be stored in the data register 2. This data is sent to the error detection/correction (ECC) circuit 3 in the refresh cycle for checking of the error. In case a correctable error (such as 1-bit error) is detected, the error bit is corrected and then written into the above-mentioned specified address as the rewriting data (DI0-DIn-1) during the refresh cycle.
JP15276679A 1979-11-26 1979-11-26 Semiconductor memory device Pending JPS5677985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15276679A JPS5677985A (en) 1979-11-26 1979-11-26 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15276679A JPS5677985A (en) 1979-11-26 1979-11-26 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5677985A true JPS5677985A (en) 1981-06-26

Family

ID=15547673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15276679A Pending JPS5677985A (en) 1979-11-26 1979-11-26 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5677985A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61117788A (en) * 1984-11-13 1986-06-05 Fujitsu Ltd Method and device for refreshing and data checking of semiconductor memory
US5375094A (en) * 1992-06-19 1994-12-20 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory system with a plurality of erase blocks
JPH0713786A (en) * 1992-11-30 1995-01-17 Internatl Business Mach Corp <Ibm> Method and apparatus for correciton of error

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61117788A (en) * 1984-11-13 1986-06-05 Fujitsu Ltd Method and device for refreshing and data checking of semiconductor memory
US5375094A (en) * 1992-06-19 1994-12-20 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory system with a plurality of erase blocks
JPH0713786A (en) * 1992-11-30 1995-01-17 Internatl Business Mach Corp <Ibm> Method and apparatus for correciton of error

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