JPS54101626A - Anomaly detection circuit for memory device - Google Patents

Anomaly detection circuit for memory device

Info

Publication number
JPS54101626A
JPS54101626A JP816078A JP816078A JPS54101626A JP S54101626 A JPS54101626 A JP S54101626A JP 816078 A JP816078 A JP 816078A JP 816078 A JP816078 A JP 816078A JP S54101626 A JPS54101626 A JP S54101626A
Authority
JP
Japan
Prior art keywords
memory
words
sub
store
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP816078A
Other languages
Japanese (ja)
Inventor
Hiroyuki Kojima
Yasuo Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP816078A priority Critical patent/JPS54101626A/en
Publication of JPS54101626A publication Critical patent/JPS54101626A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To shorten the program debug time by detecting the presence of the record of addresses corresponding to the first sub-memory and the second sub- memory when reading data as instruction words and as numeric words respectively.
CONSTITUTION: Sub-memories 3 and 4 which can store at least one bit at the corresponding address of main memory 1 are provided. Here, memory 3 is used to store the area where instruction words of memory 1 are stored and memory 4 is used to store the area where numeric words of memory 1 are stored. The presence of the record of addresses corresponding to memory 3 and memory 4 when reading contents of memory 1 as instruction words and numeric words respectively is detected, thereby shortening the program debug time greatly.
COPYRIGHT: (C)1979,JPO&Japio
JP816078A 1978-01-27 1978-01-27 Anomaly detection circuit for memory device Pending JPS54101626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP816078A JPS54101626A (en) 1978-01-27 1978-01-27 Anomaly detection circuit for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP816078A JPS54101626A (en) 1978-01-27 1978-01-27 Anomaly detection circuit for memory device

Publications (1)

Publication Number Publication Date
JPS54101626A true JPS54101626A (en) 1979-08-10

Family

ID=11685571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP816078A Pending JPS54101626A (en) 1978-01-27 1978-01-27 Anomaly detection circuit for memory device

Country Status (1)

Country Link
JP (1) JPS54101626A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6049445A (en) * 1983-08-29 1985-03-18 Indeeta Syst Kk Debug device of microprocessor or the like
JPS6044140U (en) * 1983-08-29 1985-03-28 インデ−タシステムズ株式会社 Debugging equipment for microprocessors, etc.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6049445A (en) * 1983-08-29 1985-03-18 Indeeta Syst Kk Debug device of microprocessor or the like
JPS6044140U (en) * 1983-08-29 1985-03-28 インデ−タシステムズ株式会社 Debugging equipment for microprocessors, etc.

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