JPS5547547A - Control device - Google Patents

Control device

Info

Publication number
JPS5547547A
JPS5547547A JP11950778A JP11950778A JPS5547547A JP S5547547 A JPS5547547 A JP S5547547A JP 11950778 A JP11950778 A JP 11950778A JP 11950778 A JP11950778 A JP 11950778A JP S5547547 A JPS5547547 A JP S5547547A
Authority
JP
Japan
Prior art keywords
memory
circuit
input
output circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11950778A
Other languages
Japanese (ja)
Other versions
JPS6019533B2 (en
Inventor
Kenji Shoroji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53119507A priority Critical patent/JPS6019533B2/en
Publication of JPS5547547A publication Critical patent/JPS5547547A/en
Publication of JPS6019533B2 publication Critical patent/JPS6019533B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To carry out the transmission and reception of the data of the input and output circuit and the central operation processing circuit in the same manner as those of the memory circuit and the central operation processing circuit by using a partial region of the memory circuit simultaneously with the address specification of the input and output circuit.
CONSTITUTION: When CPU outputs the address assigned to the input and output circuit 22 as an address signal 23, this is detected by the decoder 32 to control the input and output circuit 22 under the condition of the entry of the memory write signal 24 and the memory read signal 25. At this time, the memory write signal 24 and the memory read signal 25 are not outputted to the memory circuit. Then, when the test mode switch 31 is set at test mode, the memory write signal 24 and the memory read signal 25 are outputted to the memory circuit in order to data transmit the diagnosis program stored in the memory circuit 21 to CPU. At this time, the address assigned to the input and output circuit 22 is replaced by the diagnosis program, so that the memory write signal 24 and the memory read signal are not outputted to the input and output circuit 22.
COPYRIGHT: (C)1980,JPO&Japio
JP53119507A 1978-09-28 1978-09-28 Control device Expired JPS6019533B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53119507A JPS6019533B2 (en) 1978-09-28 1978-09-28 Control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53119507A JPS6019533B2 (en) 1978-09-28 1978-09-28 Control device

Publications (2)

Publication Number Publication Date
JPS5547547A true JPS5547547A (en) 1980-04-04
JPS6019533B2 JPS6019533B2 (en) 1985-05-16

Family

ID=14762964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53119507A Expired JPS6019533B2 (en) 1978-09-28 1978-09-28 Control device

Country Status (1)

Country Link
JP (1) JPS6019533B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156356A (en) * 1984-12-27 1986-07-16 Sony Corp Microcomputer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6357435A (en) * 1986-08-25 1988-03-12 Mitsui Eng & Shipbuild Co Ltd Container crane

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156356A (en) * 1984-12-27 1986-07-16 Sony Corp Microcomputer

Also Published As

Publication number Publication date
JPS6019533B2 (en) 1985-05-16

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