JPS5651074A - Address trace system - Google Patents
Address trace systemInfo
- Publication number
- JPS5651074A JPS5651074A JP12497479A JP12497479A JPS5651074A JP S5651074 A JPS5651074 A JP S5651074A JP 12497479 A JP12497479 A JP 12497479A JP 12497479 A JP12497479 A JP 12497479A JP S5651074 A JPS5651074 A JP S5651074A
- Authority
- JP
- Japan
- Prior art keywords
- address
- nonregistration
- logic block
- tlb2
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To enable high speed collection of saved address reference series data, by storing the logic block at address conversion, in nonregistration to address conversion index buffer (TLB) cleared every given time.
CONSTITUTION: When a TLB2 is cleared every given time with the output of a timer 6, the reference to different logic block afterward is handled as TLB nonregistration, the address conversion is made by referencing the conversion table on the main memory according to the nonregistration detection signal output from the TLB2, and the correspondence between the logic block and the physical address is newly registrated on the TLB2. Simultaneously, the address storage set 5 according to the nonregistration detecting signal from the TLB2 stores the program recognition number and the logic block number set on the logic address register 1 to an address buffer 51. Thus, the logic block at nonregistration is sequentially stored in the set 5 and it is written out to an external memory unit via the set 5 in the same order, allowing to collect the saved address reference series data in high speed.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12497479A JPS5651074A (en) | 1979-09-28 | 1979-09-28 | Address trace system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12497479A JPS5651074A (en) | 1979-09-28 | 1979-09-28 | Address trace system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5651074A true JPS5651074A (en) | 1981-05-08 |
JPH0118458B2 JPH0118458B2 (en) | 1989-04-05 |
Family
ID=14898814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12497479A Granted JPS5651074A (en) | 1979-09-28 | 1979-09-28 | Address trace system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5651074A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6269332A (en) * | 1985-09-21 | 1987-03-30 | Nec Corp | Storing system for history information |
JP2012518234A (en) * | 2009-02-19 | 2012-08-09 | フリースケール セミコンダクター インコーポレイテッド | Generation of address translation trace messages for debugging |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5275938A (en) * | 1975-12-18 | 1977-06-25 | Ibm | Memory hierarchy system |
-
1979
- 1979-09-28 JP JP12497479A patent/JPS5651074A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5275938A (en) * | 1975-12-18 | 1977-06-25 | Ibm | Memory hierarchy system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6269332A (en) * | 1985-09-21 | 1987-03-30 | Nec Corp | Storing system for history information |
JP2012518234A (en) * | 2009-02-19 | 2012-08-09 | フリースケール セミコンダクター インコーポレイテッド | Generation of address translation trace messages for debugging |
Also Published As
Publication number | Publication date |
---|---|
JPH0118458B2 (en) | 1989-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5629769A (en) | Word storing system | |
JPS56140451A (en) | Log information holding device | |
JPS55157181A (en) | Buffer memory control system | |
JPS5680872A (en) | Buffer memory control system | |
JPS5651074A (en) | Address trace system | |
JPS53122327A (en) | Bar code reader | |
JPS55163697A (en) | Memory device | |
JPS55124862A (en) | Frequency control unit | |
JPS55113200A (en) | Checking method for ic memory | |
JPS57157369A (en) | Loop tracking processing system | |
JPS55105719A (en) | Buffer device | |
JPS5637892A (en) | Memory unit | |
JPS55105884A (en) | Address conversion device | |
JPS5661096A (en) | Error detection system for read only memory electrically erasable | |
JPS5654677A (en) | Associative memory device | |
JPS5580900A (en) | Memory device | |
JPS5622151A (en) | Branch address recording system | |
JPS54101626A (en) | Anomaly detection circuit for memory device | |
JPS5578357A (en) | Program overrun detection unit | |
JPS5644180A (en) | Information retrieval device | |
JPS5448128A (en) | Buffer memory unit | |
JPS5450240A (en) | Information processing unit | |
JPS5552598A (en) | Data processor | |
JPS5619158A (en) | Logic tracer | |
JPS55140944A (en) | Microorder address storing device |