JPS6269332A - Storing system for history information - Google Patents

Abstract

PURPOSE:To obtain quickly the data that is effective for study of the factor of a fault by storing successively the information on the replacement of the address converting information in the form of the history information. CONSTITUTION:A main memory 1 includes a pointer area 2 and a firmware FW work area 3. The area 2 contains an FW stack pointer 4 of 4 bytes starting at an address of 20H (sexadecimal digit) for example. The pointer 4 is provided with an address indicating an FW stack area 5 included in the area 3, a trace mode bit showing whether the history information is stored or not and a log-out display bit showing whether or not the stored history information is set in a log-out mode. The area 5 contains an areas that correspond to each CPU and have the same capacity. Then the factors of a fault can be checked and analyzed quickly and accurately by means of the history information.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention Industrial Application Field The present invention relates to an information processing system having a conversion mechanism from a logical address to an absolute address. The present invention relates to a history information storage device for recording information.

BACKGROUND OF THE INVENTION Information processing systems including computers are commonly used in fields such as data processing and data communications. In recent years, such information processing systems have become increasingly complex and include increasingly sophisticated functions.

In particular, in a virtual memory system that requires address translation from a logical address on a program to an absolute address on a main memory, hardware, firmware, and software are intricately intertwined.

Problems to be Solved by the Invention In the above-mentioned complex information processing system, it is often extremely difficult to investigate and analyze failures that occur during operation, and to determine the cause.

In particular, in a multiprocessor system consisting of a plurality of computer systems, it is even more difficult to investigate and analyze the cause of the failure.

That is, there is a problem in that it requires a great deal of effort and time to investigate and analyze the causes of such failures and attempt to resolve them.

Structure of the Invention Means for Solving the Problems The method of the present invention for solving the problems of the prior art described above is to store update processing information of address translation information for executing each address translation software command group as history information. When it is determined that storage operation is specified, history information and time information are sequentially stored, and this history information can be used to quickly and reliably investigate and analyze the cause of the failure. It is configured so that it can be done.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment 1 FIG. 1A is a main memory configuration diagram in an information processing system to which an embodiment of the present invention is applied.

This main memory 1 includes a pointer area 2 and firmware (
It has a work area 3 (abbreviated as rFWJ).

The pointer area 2 has a 4-byte FW stack pointer 4 starting from address 20H (], hexadecimal number), for example.

The FW stack pointer 4 includes an address that points to the FW stack area 5 included in the FW work area 3, a trace mode bit that indicates whether or not history information is to be stored, and a trace mode bit that indicates whether or not the stored history information is being logged out. Consists of logout display bits.

The FW star area 5 consists of areas with the same capacity corresponding to each central processing unit (rCPUJ). That is, they are a CPU#O area 6, a CPU#1 area 7, a CPU#2 area 8, and a CPU#3 area 9.

The CPU #Oi1 area 6 contains a pointer lO for identifying the CPU, and storage areas #11 and #2 for history information of 2"-1 pieces.
Consisting of 2...# (2"-1).

In each storage area, as illustrated in FIG. 1(B), the type of executed instruction and the task name at that time are stored.

Contents of instruction counter, contents of general-purpose register G1.

The contents of general-purpose register G1+1 and time information TOD are respectively stored.

CPU #1 area 7. CPU #2 area 8 and cpU #
The 38W area 9 is also configured exactly the same as the CPU #0 area 6 described above.

FIG. 2 is a diagram illustrating the format of instructions related to address translation information update control. In the figure, an instruction consists of 16 bits, including an 8-bit instruction code and 4-bit general-purpose register numbers G1 and 62.

FIG. 3 is a diagram for explaining the types of general-purpose registers involved in address translation information update control, and shows the types of general-purpose registers GR for each instruction.

5TGSD instruction uses general purpose registers GI G2 and G2+
Use 1. General-purpose register G1 consists of a segment number SEG# of 0th to 15th bits and a task name of 16th to 31st bits. General-purpose register G2 is the first word of segment descriptor SD, and similarly general-purpose register G2+
1 is the second word of the segment descriptor SD.

The 5TGPD instruction uses general purpose registers C1, G1+1 and G
Use 2. In the general-purpose register G1, the 0th to 15th bits are undefined, and the 16th to 31st bits are the task name. In the general-purpose register G1+1, the 0th to 15th bits are the segment number SEG#, the 16th to 19th bits are the page number P#, and the 20th to 31st bits are undefined. General purpose register G2 is a page descriptor PD.

The R3TSD instruction uses general purpose registers G1 and G2. General-purpose register G1 is the same as general-purpose register G1 used by the 5TGSD instruction. General-purpose register G2 is the Oth
The ~7th bin is the reset mask RM, and the 8th~31st
Bit is undefined.

The R5TPD instruction uses general purpose registers G1, G1+1 and G
Use 2. The types of general-purpose registers G1 and 01+1 are each the same as the general-purpose registers of the same number used by the 5TGPD instruction. Also, the model of general-purpose register G2 is R3T.
It is the same as that used by the SD instruction.

The CLHR3 instruction uses only general purpose register G1, and general purpose register G2 is undefined. General-purpose register 01 is
It is the same as that used by the 5TGSD instruction.

FIG. 4 is a flowchart illustrating the contents of history information storage processing performed in conjunction with the 5TGSD command and the 5TGPD command.

In the first step 3I, the type of instruction is determined. If it is a 5TGSD instruction, in step 32, the absolute address W of the segment descriptor SD specified by the general-purpose register G1 related to this instruction is determined. In the next step 33, the contents of general purpose registers G2 and G2+1 relating to the same <5TGSD instruction are stored in the 8-byte main memory starting from the above absolute address W.

On the other hand, if the determination result in step 31 is a 5TGPD instruction, then in step 34, the absolute address W of the page descriptor PD specified by general-purpose registers G1 and G1+1 related to this 5TGPD instruction is determined. In the next step 33, the contents of the general-purpose register G2 related to the same <5TGPD instruction are stored in the 4-byte main memory starting from the above-mentioned absolute address W.

After executing the above 5TGSD instruction or 5TGPD instruction,
At step 36, historical information is stored. The storage process of this history information will be described in detail later with reference to FIG. In the last step 37, the instruction counter IC
is incremented by 2.

FIG. 5 shows R3TSD and R3TPD instructions.

Contents of CLHR3 command and CLHRP command and multiple CP
3 is a flowchart showing a response procedure between U;

First, in steps 41 and 42, an instruction to lock communication between 020 and its confirmation is performed. Next step 43
At step 44, a communication command (PAUSE) for temporarily halting the execution of instructions to all other CPUs is sent, and a response thereto is confirmed. Responding side CP
The operation of U will be explained later with reference to FIG.

In the next step 45, the type of instruction is determined and R
3TSD instruction or CLHR3 instruction, step 4
6 and send the communication command CLR3 to all other CPUs.
D is sent. The operation of the CPU on the receiving side of this command will be explained later with reference to FIG. In the next step 47, it is determined whether the instruction is an RSTSD instruction or a CLHR3 instruction, and if the instruction is an R3TSD instruction, the process proceeds to step 48, and if it is a CLHR3 instruction, the process proceeds to step 50.

In step 48, the absolute address W of the segment descriptor SD specified by the general-purpose register G1 related to the R3TSD instruction is determined. In the next step 49, in accordance with the cent mask RM specified by the general register G2 related to this R3TSD instruction, the absolute address W is
The bit in the hide pointed to by is reset. Further, in step 50, information regarding the segment specified by the general-purpose register G1 related to this R3TSD instruction is cleared from the address translation buffer TLB for performing high-speed translation from a logical address to an absolute address. A similar clearing process is performed on the CL in the next step 50.
This is also done for HRS commands. That is, CLHR
Information regarding the segment specified by the general-purpose register G1 related to the 5 instructions is cleared from the address translation buffer TLB.

On the other hand, in step 45, the R3TPD instruction or the CL
If it is determined that it is an HRP command, the process proceeds to step 51.
and then send the communication command CL to all other CPUs.
RPG is sent out. The operations of other CPUs that have received this will be detailed later. In the next step 52, it is determined whether the instruction is an R3TPD instruction or a CLHRP instruction, and if it is an R3TPD instruction, the process proceeds to step 53.
If it is a CLHRP command, the process goes to step 55.
to move to.

In step 53, the absolute address W of the page descriptor PD specified by the general-purpose registers G1 and CI+1 related to the RSTPD instruction is determined. In the next step 54, the bit in the hide indicated by the absolute address W is reset according to the reset mask RM specified by the general-purpose register G2 related to this R8TPD instruction.

Furthermore, in step 55, information regarding the page specified by general-purpose registers G1 and G1+1 related to this R3TPD instruction is cleared from address translation buffer T1□B. Clearing processing similar to this is performed in the next step 55.
This is also done for the CLHRP instruction. In other words, general-purpose registers G1 and G related to the CL HRS instruction
Information regarding the page specified by 1+1 is cleared from the address translation buffer TLB.

R3TSD instruction and R3TPD instruction as described above.

When either one of the CL HRS and CLHRP instructions is executed, processing moves to step 56 where historical information is stored.

In the next step 57, from all other CPUs,
In steps 46 and 51, waiting is performed until a response to the communication instruction issued for each command type is returned. When this response is returned, the process moves to the next step 58,
Here, the communication command FR for releasing the PAUSE sent to all other CP[J in step 43
When the EE is sent and the response thereto is confirmed in the next step 59, the communication lock is released in step 60. At the final step 61, the instruction counter IC is incremented by 2, and then the entire process ends.

FIG. 6 is a flowchart illustrating the operation of the CPU on the receiving side in response to the various communication commands issued to all other CPUs in steps 43, 46 and 51 of FIG.

First, in steps 71 and 713, the communication command P
AUSE is received and a response thereto is performed. In the next step 72, a wait is made for the aforementioned communication commands CLR3D and CLRPG, and when one of them is received, in step 72 it is determined which communication command it is. The next process moves to step 74 if this communication command is CLR3D, and moves to step 75 if it is CLRPG.

In step 74, information regarding the segment specified by the communication command CL R3D is cleared from the address translation buffer TLB. Similarly, in step 75, information regarding the page specified by the communication command CLRPG communication is cleared from the address translation buffer TLB.

When the above-described CLR3D and CLRPD command processing is completed, history information is recorded in step 76.

In the next step 77, the completion of storing the history information is reported to the transmission (!111 CPU), and in the next steps 78 and 79, the transmission source sends a communication command FR.
An EE is waited for and a response thereto is made.

FIG. 7 shows step 36 of FIG. Step 5 in Figure 5
7 is a flowchart illustrating the history record ↑O process performed in step 6 and step 76 of FIG. 6, that is, the storage process of history information regarding update of address conversion information.

In a first step 81, the main memory 1 shown in FIG.
The contents of address 20H are set to Xo. In the next step 82, it is determined whether the arrangement of the 0th bit and the 1st bit of the XO is 10''. That is,
The 0th bit of this Xo is a trace mode bit, and its "l" instructs storage of history information. Also, X
The first bit of o is a logout indication bit, and "0" indicates that the log alerts 1 through 1 of the stored history information are not being executed. During logout, registration of new history information is excluded in order to fix the history information.

In step 83, the CPU number (in this case, CPU#=0 to 3) is added to the address part X of the FW stack pointer 4 in FIG. and 214 are added, and this added value is set as Y. That is, each CP
For U, a 214-byte main memory area is allocated, and the above Y means the start address of the main memory area allocated to each CPU specified by CPU#.

In the next step 84, the CPU# and "4" are added to the above X.
'' is added, and the content of the main memory with this added value as the address is set to Z. In other words, in the pointer 10 of FIG. 1, each CPU's pointer has a 4-byte area, so the above Z is This is a pointer to each CPU specified by CPU#.Here, if Z is given a relative address to Y above, Y+Z specifies the storage start address of the history information of the CPU specified by CPU#. become.

In step 85, the command code of the history information to be stored, the distinction between commands and communication (processing in the own CPU and processing in other CPUs),
The processing distinction in U) and the task name to which this instruction belongs are stored in the 4 bytes starting from the above address Y+Z.

After 4 is added to Z in step 86, step 87
The contents of the instruction counter IC are stored in 4 bytes starting from address Y+Z. After 4 is added to Z again in step 88, the contents of general-purpose register G1 are stored in the 4-hide area starting from address Y+Z in step 89.

After 4 is further added to the above Z in step 90, the contents of general-purpose register G1+1 are changed to address Y in step 91.
It is stored in a 4-byte area starting from +Z.

After 4 is added to Z in step 92, step 93
．． At 94 and 95, the value of time information TOD is stored in the following 8-byte area.

Through the processing operations so far, information regarding the address conversion information update operation and its time information are stored in one storage area illustrated in FIG. 1(B). ITOD is stored as one piece of history information.

After that, in step 97, 12 is added to Z, and then in step 97, it is determined whether Z has reached 214 or not. If Z has reached 214, it is determined that the main memory area given to that CPU# is gone, and Z is set to its initial value of 32 in step 9B.

As a result, the next history information is stored in the first storage history #1.

On the other hand, if Z has not reached 214, the process moves to step 99, where Z is assigned to the CPU specified by CPU#.
as a pointer to the pointer's storage address (X0C
Store in PU#・4).

In this way, history information regarding address translation information update operations can be distinguished and sequentially stored for each CPU.

An embodiment of the present invention has been described above, taking as an example the case where there are four CPUs, but in general, the number of CPUs can be m (m≧1).

Effects of the Invention As explained in detail above, the history information storage method of the present invention is configured to sequentially store information related to updates of address translation information as history information, so HW, FW, and SW are complicatedly intertwined. When such a failure occurs, this historical information can be read and data useful for investigating the cause of the failure can be quickly provided.

[Brief explanation of drawings]

FIGS. 1A and 1B are configuration diagrams of a main memory in an information processing system to which an embodiment of the present invention is applied. FIGS. 2 and 3 are conceptual diagrams illustrating the types of software instruction groups and general-purpose register types for updating address conversion information, respectively, and FIGS. 4 and 5 (A). (B), (C), Figure 6, Figure 7 (A), (B
) is a flowchart explaining the operation of the above embodiment. 1... Main memory, 2... Pointer area, 3... FW work distribution area, 4... FW Sukunokubo ink. 5...FW stack area.

Claims (1)

[Scope of Claims] In an information processing system having an address conversion mechanism that converts a logical address on a program to an absolute address on the main memory when accessing the main memory, each of the address conversion software instructions is executed. It is characterized by checking designation information as to whether update processing information of address conversion information to be stored should be stored as history information, and sequentially storing the history information and time information when it is determined that storage operation is designated. historical information storage method.