JPS5622291A - Bit error correction method for memory - Google Patents
Bit error correction method for memoryInfo
- Publication number
- JPS5622291A JPS5622291A JP9675479A JP9675479A JPS5622291A JP S5622291 A JPS5622291 A JP S5622291A JP 9675479 A JP9675479 A JP 9675479A JP 9675479 A JP9675479 A JP 9675479A JP S5622291 A JPS5622291 A JP S5622291A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- register
- correction data
- address
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To simplify the control circuit or the like in the memory, by performing the rewrite-in of correction data of error bit with CPU.
CONSTITUTION: If bit error is taken place in the momory area 11 of the memory 1, this error bit is detected at the ECC circuit 13 and the circuit 13 feeds the bit error signal to the address save register 12 and the interruption control circuit 22 of CPU2. Thus, the correction data from the circuit 13 is set to the read buffer 23 and write buffer 24. Next, the address stored in the register 12 is set to the buffer 23 and the address register 21. Further, in the memory area 11, the correction data stored in the buffer 24 is written in the memory location of the address set to the register 21. Thus, the production of correction data and the detection of error bit are made in the memory 1 and on the other hand, the rewrite-in operation control of the corrected data is made in CPU2.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54096754A JPS6024492B2 (en) | 1979-07-31 | 1979-07-31 | memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54096754A JPS6024492B2 (en) | 1979-07-31 | 1979-07-31 | memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5622291A true JPS5622291A (en) | 1981-03-02 |
JPS6024492B2 JPS6024492B2 (en) | 1985-06-13 |
Family
ID=14173442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54096754A Expired JPS6024492B2 (en) | 1979-07-31 | 1979-07-31 | memory system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6024492B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57172402A (en) * | 1981-04-17 | 1982-10-23 | Sony Corp | System control circuit |
JPS5823399A (en) * | 1981-08-03 | 1983-02-12 | Nec Corp | Main storage device |
JPS63282872A (en) * | 1987-05-15 | 1988-11-18 | Fujitsu Ltd | Data processor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0237511Y2 (en) * | 1985-09-02 | 1990-10-11 |
-
1979
- 1979-07-31 JP JP54096754A patent/JPS6024492B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57172402A (en) * | 1981-04-17 | 1982-10-23 | Sony Corp | System control circuit |
JPS5823399A (en) * | 1981-08-03 | 1983-02-12 | Nec Corp | Main storage device |
JPS63282872A (en) * | 1987-05-15 | 1988-11-18 | Fujitsu Ltd | Data processor |
Also Published As
Publication number | Publication date |
---|---|
JPS6024492B2 (en) | 1985-06-13 |
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