JPS63282872A - Data processor - Google Patents

Data processor

Info

Publication number
JPS63282872A
JPS63282872A JP62117027A JP11702787A JPS63282872A JP S63282872 A JPS63282872 A JP S63282872A JP 62117027 A JP62117027 A JP 62117027A JP 11702787 A JP11702787 A JP 11702787A JP S63282872 A JPS63282872 A JP S63282872A
Authority
JP
Japan
Prior art keywords
cpu
circuit
data transfer
bit error
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62117027A
Other languages
Japanese (ja)
Inventor
Kazuo Sumiya
Hiroki Masuda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62117027A priority Critical patent/JPS63282872A/en
Publication of JPS63282872A publication Critical patent/JPS63282872A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To inhibit the transmission of one-bit error detection during DMA data transfer to a CPU by suppressing an one-bit error detecting signal outputted from an ECC circuit having an one-bit error detecting/correcting function by a DMA data transfer signal outputted from the CPU. CONSTITUTION:A main memory device 1 has a detecting/correcting circuit (ECC circuit) 10 having the one-bit detecting and correcting function and a memory part 20. A DMA control circuit 3 is allowed to execute the I/O of data to/from the main memory device 1 independently of the instruction executing operation of the CPU 2. When a signal indicating direct data transfer is outputted from the CPU 2, a signal suppressing circuit 4 inhibits the transmission of an one-bit error detecting signal from the circuit 10 to the CPU 2. Even if the one-bit error is detected by the circuit 10 during the DMA data transfer, the error detecting signal is not transmitted from the ECC circuit 10 to the CPU 2 only during the DMA data transfer.
JP62117027A 1987-05-15 1987-05-15 Data processor Pending JPS63282872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62117027A JPS63282872A (en) 1987-05-15 1987-05-15 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62117027A JPS63282872A (en) 1987-05-15 1987-05-15 Data processor

Publications (1)

Publication Number Publication Date
JPS63282872A true JPS63282872A (en) 1988-11-18

Family

ID=14701632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62117027A Pending JPS63282872A (en) 1987-05-15 1987-05-15 Data processor

Country Status (1)

Country Link
JP (1) JPS63282872A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617442A (en) * 1979-07-21 1981-02-19 Nippon Telegr & Teleph Corp <Ntt> Parity error processing system
JPS5622291A (en) * 1979-07-31 1981-03-02 Fujitsu Ltd Bit error correction method for memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617442A (en) * 1979-07-21 1981-02-19 Nippon Telegr & Teleph Corp <Ntt> Parity error processing system
JPS5622291A (en) * 1979-07-31 1981-03-02 Fujitsu Ltd Bit error correction method for memory

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