JPS63282872A - Data processor - Google Patents

Abstract

PURPOSE:To inhibit the transmission of one-bit error detection during DMA data transfer to a CPU by suppressing an one-bit error detecting signal outputted from an ECC circuit having an one-bit error detecting/correcting function by a DMA data transfer signal outputted from the CPU. CONSTITUTION:A main memory device 1 has a detecting/correcting circuit (ECC circuit) 10 having the one-bit detecting and correcting function and a memory part 20. A DMA control circuit 3 is allowed to execute the I/O of data to/from the main memory device 1 independently of the instruction executing operation of the CPU 2. When a signal indicating direct data transfer is outputted from the CPU 2, a signal suppressing circuit 4 inhibits the transmission of an one-bit error detecting signal from the circuit 10 to the CPU 2. Even if the one-bit error is detected by the circuit 10 during the DMA data transfer, the error detecting signal is not transmitted from the ECC circuit 10 to the CPU 2 only during the DMA data transfer.

Description

[Detailed Description of the Invention] [Summary] The 1-bit error detection signal of the ECC circuit, which has a 1-bit error detection/correction function, is suppressed by the DMA data transfer in progress signal from the central processing unit, and the 1-bit error detection signal during DMA data transfer is suppressed. This is a data processing device that does not transmit error detection to the central processing unit.

[Industrial application field]

The present invention relates to a data processing device, and more particularly to control of a 1-bit error detection signal during DMA data transfer in a main memory device having a 1-bit error detection/correction function.

-i, the term DMA (direct memory access) is used in contrast to the term program control mode, in which each operation is controlled by a central processing unit program.
In DMA mode, data transfer occurs directly between main storage and input/output devices without central processing unit intervention. That is, in the program control mode, the central processing unit stores data in its own accumulator and executes data transfer, and in the DMA mode, the central processing unit executes data transfer by issuing only commands.

When the central processing unit starts the DMA mode, the central processing unit first sets information for performing DMA data transfer in the DMA control unit in the program control mode. This information consists of ■the amount of data to be transferred (sometimes it is given in words and sometimes it is given in bytes, but in either case, information on how many words (bytes) to send), ■memory address (memory space Control information (information indicating the direction of data transfer, whether input or output). Additionally, the central processing unit provides commands to the input/output devices. When this information is given, the given input/output device and DMA control device perform data transfer in accordance with this information, independently of the command operation of the central processing unit.

When DMA is started, the central processing unit halts. Meanwhile, data is transferred between the main storage device and the input/output device according to the information. During this time, the central processing unit remains in a halt state.

When the data transfer is completed, the central processing unit starts operating and resumes the program control mode from the next command that was halted.

Such data transfer requires accuracy of the transferred data.

[Conventional technology]

The storage section (memory) of the main storage device is composed of D-RAM (dynamic RAM). There is a temporary failure that does not make it unusable, such as bit destruction (memory destruction) caused by alpha rays.

This failure occurs with a certain probability, but in order to correct it, an ECC circuit (error correcting and checking circuit) is conventionally provided.

ECC circuits generally detect and correct 1-bit errors in data read from memory, but when there are 2 or more bits of errors, they are configured to only detect and not correct them. It is something. In other words, when focusing on a certain word in memory, if one bit here becomes a fault, this fault will be detected by the ECC circuit when reading data, and the ECC circuit will correct the fault to the original correct value. Output. At the same time, the ECC circuit generates an interrupt to the central processing unit when it detects an error in the data in the memory.

When this interrupt occurs in the central processing unit, the affected data restoration program stores the correct data held in the ECC circuit at the address where the information error was detected. In this way, even erroneous data in the main memory is corrected to a correct value by the processing of the central processing unit.

[Problem that the invention seeks to solve]

However, with conventional data processing devices, as mentioned above,
Even though the data contents are guaranteed during data transfer due to the data correction process of the ECC circuit, the data transfer is stopped midway, the central processing unit is released from the halt state, and the error location in the memory is corrected. Performing data correction. In other words, the data transfer is progressing well and there is no necessity to stop the data transfer, but the data transfer is stopped and the error location in the memory is corrected.

It is true that from the perspective of fixing the memory, it is good because it fixes it quickly, but stopping data transfer even though normal data is being transferred means having to start the data transfer all over again. However, there is a problem in that it results in a large loss of time.

This problem does not occur if the data transfer is resumed from where it left off, but this process requires very difficult software processing.

The present invention was made based on the fact that even if an error is discovered in the data during DMA data transfer, the data output from the ECC circuit is guaranteed, and its purpose is to , even if there is an error in the data during DMA transfer, the error is ignored, i.e. D
Even if an error is detected in the data during MA data transfer,
It is an object of the present invention to provide a data processing device that notifies the central processing unit of the detection of an error in data after DMA transfer ends, without informing the central processing unit of the detection result.

[Means for solving problems]

FIG. 1 shows a basic diagram of the data processing apparatus of the present invention.

In the figure, 1 is a main memory device, which includes a detection/correction circuit 10 (ECC circuit) having a 1-bit error detection function and correction function, and a storage section 20. 2 is a central processing unit that executes instructions. 3 is a DMA control circuit;
Data input/output to the main memory device 1 can be executed independently of the instruction execution operation of the central processing unit 2. Reference numeral 4 denotes a signal suppression circuit, which prohibits transmission of the 1-bit error detection signal from the detection/correction circuit 10 to the central processing unit 2 when there is a signal indicating that data is being directly transferred from the central processing unit 2. do. 5 is an input/output device, 6 is a peripheral device, and 8 is a pass line.

[Effect]

According to the data processing device of the present invention, even if a 1-bit error is detected in the data by the ECC circuit during DMA data transfer, the error detection signal is emitted only during DMA data transfer.
It is not transmitted from the CC circuit to the central processing unit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows the configuration of an embodiment of the data processing apparatus of the present invention.

In the figure, 1 is a main memory device, which includes an ECC circuit 10 which is a detection/correction circuit having a function of detecting and correcting a 1-bit error, and a memory 2° which is a storage section. 2 is a central processing unit that executes instructions. Reference numeral 3 denotes a DMA control circuit within the central processing bag W2, which can input and output data to the main storage device 1 independently of the instruction execution operation of the central processing unit 2.

Reference numeral 4 denotes a signal suppression circuit, which in this embodiment is composed of an AND gate 4a having a positive logic input and a negative logic input. The positive logic input of the AND gate 4a is connected to the output terminal of the 1-bit error detection signal in the ECC circuit 10, and the negative logic input is connected to the output terminal of the DMA device 3 for a signal indicating that DMA data is being transferred. The output terminal of this AND gate 4a is connected to the interrupt bit terminal 2a of the central processing unit 2.

The main memory device I and central processing unit 2 are connected to a processor bus 8a. A peripheral bus 8b is connected to the processor bus 8a, and a file memory control device 5a, a data communication control device 5b, etc. are connected as input/output devices to this peripheral bus 8b. Peripheral devices such as a floppy disk device 6a and a hard disk device 6b are connected to the file memory control device 5a, and data is transferred to and from the main storage device 1 under write/read control of the file memory control device 5a. In addition, the hard disk device 5
A maintenance console 6c, etc. is connected to b, and by transferring data with the main storage device 1, it inputs and outputs commands and messages for operation, maintenance management, and work of this data processing device. .

In the data processing device configured as described above, DMA data transfer is performed between the main storage device 1 and peripheral devices such as the floppy disk device 6a, the hard disk device ff6b, or the maintenance console 60 according to commands from the DMA control circuit 3. Then, during DMA data transfer, the ECC circuit 10
detects 1 bit F of data, the ECC circuit 10
corrects the data to a correct value and outputs a 1-bit error detection signal to its output terminal. This 1-bit error detection signal is transmitted to the positive logic input of AND circuit 4a.

On the other hand, a signal indicating that DMA data is being transferred is output from the DMA device 3 to the negative logic input of the AND circuit 4a. Therefore, at this time, the output of the AND circuit 4a is the ECC circuit 1.
The 1-bit error detection signal from 0 does not appear, and this signal is not transmitted to interrupt bit 2a of central processing bag W2.

As a result, even if the ECC circuit 10 detects a 1-bit error in the transferred data during DMA data transfer, the detection signal is not transmitted to the central processing unit 2, and therefore, the DMA data transfer ends. will be carried out reliably. Then, when the DMA data transfer is completed, there is no output from the DMA control circuit 3 to the negative logic input of the AND circuit 4a, so that the l bit error detection signal from the ECC circuit 10 is
This appears at the output of the ND circuit 4a, and is transmitted to the interrupt bit 2a of the central processing unit 2, and the central processing unit 2 corrects the erroneous data in the main memory 1. This process will be explained using FIG. 3.

FIG. 3 shows in detail the configuration of the main memory device 1 including the ECC circuit 10 and the central processing unit 2. As shown in FIG.

In FIG. 3, 1 is the main memory, 2 is the central processing unit,
2a is an interrupt bit, 3 is a DMA control circuit, 4 is a signal suppression circuit, 4a is an AND circuit, 10 is an ECC circuit, 20 is a memory, 31.32 is a write data line (m bits) from a processor bus 8a (not shown). ), 12 is a check bit generation circuit, 33 is a check bit data line (n bits),
21 is a write data register (write data + check bit = m + n bits), 22 is a memory array section, 2
3 is a read data register (sequential data + check pit = m + n bits), 34 is a continuous check bit line (n bits), and 35 is a memory read data line (m bits).
, 13 is a memory read/write control circuit, 14 is a syndrome generation circuit, 36 is a syndrome line, 15 is a syndrome decode circuit, 16 is an error detection circuit, 17 is a data correction circuit, and 37 is a corrected memory continuation data line. be.

First, DMA data transfer in the write direction by the DMA control circuit 3 will be described. Write data sent from a processor bus 8a (not shown) is sent through a write data line 31 to a check bit generation circuit 12, which will be described later, to generate check bits (check bits are n bits, so C0~
C+t-+) is generated. By combining this check bit and the write data, an m+n bit code word is generated and written to the memory array section 22 via the write data register 21. This is the write operation of DMA data transfer.

Next, the DM in the read direction by the DMA control circuit 3
A data transfer will be explained. m + n, which is the code word stored in the memory array section 22 during the read operation.
The bits are read out and taken into successive data register 23. The data part and check bit part in this code word are sent to the syndrome generation circuit 14, and only the data part is sent to the data correction circuit 17.

In the syndrome generation circuit 14, check bits (n bits) are created from the data section in the same way as when check bits were generated in the write check pit generation circuit 12, and this result and the read check bits (n bits) are This result is the syndrome S0~Sn
-1. As a result of the comparison, if each bit of the syndrome is all "0", it means that there is no error, and if any one bit or more is "1", it means that there is an error.

This syndrome (n bits) is transmitted to the syndrome decode circuit 15 and the error detection circuit 1 by the syndrome line 36.
6 is sent out. In the syndrome decoding circuit 15, the above-mentioned 30 to S? l-1 is input to a decoder, and in the case of a 1-bit error, the position of the error bit is detected from the output of this decoder. The position of this error bit is outputted to the data correction circuit 17 and corrected by inverting the error bit of the successive data that was output from the successive data register 23 that was sent out earlier.

The corrected data section is connected to the corrected memory read data line 37.
The signal is sent to the processor bus 8a and sent to the input/output circuit.

The ECC circuit 10 operates as described above, and when it detects a 1-bit error in the read data while continuously outputting data to the memory array section, the data correction circuit 17 corrects it and outputs it, and also outputs the 1-bit error. The error detection signal is held in the error detection circuit 16.

This one-bit error detection signal is transmitted to the interrupt bit 2a of the central processing unit 2 via the signal suppression circuit 4. on the other hand,
During DMA data transfer, the negative logic input of the AND circuit 4a of the signal suppression circuit 4 receives the DMA data from the DMA control circuit 3.
Since the signal indicating that data is being transferred is input, the signal from the error detection circuit 16 is not output from the signal suppression circuit 4 only during DMA data transfer.

DMA transfer is completed and DMA? When the signal from the IIJ control circuit 3 to the signal suppression circuit 4 disappears, the 1-bit error detection signal from the error detection circuit 16 is transmitted to the interrupt pin 2a of the central processing unit 2 via the signal suppression circuit 4. Therefore, the central processing unit 2 reads out the corrected memory successive data held in the data correction circuit 17 via the processor bus 8a by interrupt processing, and sends it to the memory array unit via the processor bus 8a and the write data line 32. The location where the 1-bit error of 22 has occurred is corrected using this correct data.

As described above, in the present invention, even if a 1-bit error is detected in the transfer data during DMA data transfer, the DMA data transfer is not interrupted and is executed to the end.

〔Effect of the invention〕

As explained above, in the data processing device of the present invention, the DM
A 1-bit error in the storage data in the main storage device 1 detected during data transfer is corrected after the DMA data transfer is completed, so that the DMA data transfer is not interrupted midway (, This has the effect of making it possible to improve time efficiency by eliminating the need to re-transfer data from the beginning.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the data processing device of the present invention, FIG. 2 is a block diagram of an embodiment of the data processing device of the present invention, and FIG. 3 is the main storage device, central processing unit, and signal FIG. 2 is a block circuit diagram showing a detailed configuration of a suppression circuit. 1... Main storage device, 2... Central processing unit, 3...
DMA control circuit, 4...signal suppression circuit, 4a...A
ND circuit, IO...ECC circuit, 20...memory. Principle block diagram of the present invention Fig. 1 Fig. 2

Claims (1)

[Scope of Claims] A main storage device (1) equipped with a detection/correction circuit (10) having a 1-bit error detection function and a correction function, a central processing unit (2), and the main storage device (1). D that can directly input and output data to and from the computer without going through the central processing unit (2);
The MA control circuit (3) and the 1-bit error detection signal from the detection/correction circuit (10) are transmitted to the central processing unit when there is a signal indicating that data is being directly transferred from the central processing unit (2). (2) and a signal inhibiting circuit (4) for inhibiting transmission;
After the operation of the A control circuit (3) is completed, the 1-bit error detection signal is transmitted to the central processing unit (2), and the 1-bit error in the main storage device (1) is corrected by the central processing unit (2). data processing device.