JP2891897B2 - Store-in cache failure handling system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a store-in cache of a shared memory type multiprocessor system, and more particularly to a store-in cache failure processing system.

[0002]

2. Description of the Related Art In a failure processing system for a store-in cache, when a parity error is detected when data is written to a cache, or when a hardware failure such as a value of an address register causing a parity error occurs, an illegal operation is performed. Since such data is read / written, if such a failure is detected, data consistency cannot be guaranteed in the entire system, and processing for stopping the system has been performed.

[0003]

In the conventional store-in cache fault handling system described above, as a result of being controlled by the store-in method, "the latest data in the entire system exists not in the main memory but in the main cache. When a failure is detected due to a hardware failure, the system often needs to be stopped to ensure data consistency, resulting in poor system utilization. there were.

[0004]

A store-in cache fault system according to the present invention is a store-in cache fault processing system for a shared memory multiprocessor system, wherein data indicating a byte position of data to be written to the cache is provided. (WBP) from buffer to W
When the BP is read, the parity error of the WBP is detected, and when the parity error is detected, the value of the WBP is masked to a value of “0”, and the parity error is not detected.
Mask means for sometimes outputting the value of the read WBP ;
First parity check means for parity-checking the output of a write data register for holding data to be written to the cache, and second parity checking means for parity-checking the output of a merge register for holding data once read from the cache. Check means, from the output of the first parity check and the output of the second parity check and a signal indicating that the cache registration operation is being performed,
Instructing means for instructing the code for 1-bit error correction / 2-bit error detection to be written to the cache to appear as a 2-bit error, and performing 1-bit error correction / 2-bit error detection for the data to be written to the cache. And a means for processing the code so that the code looks like a two-bit error and outputs the processed code if there is an instruction from the instruction means.
When a bit error has occurred, the data is corrected and parity is correctly given. When a two-bit error occurs, parity is given so that a parity error occurs. Third parity check means for parity checking the output of the address register designating the entry; and a write instruction for the cache based on the output of the third parity check means and a signal designating the timing of writing to the cache. and a suppression means for suppressing that, selector
Mask means selected by the data and held in the register
Fourth parity check to check the output from
And a click means, said first, second, and third parity
Notify the corresponding request source of the error result of the check means
Entrusts the processing of the request source to the fourth parity checker
The error result of the stage is the multiprocessor system stoppage.
It is characterized in that you use to.

[0005]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a store-in-cache failure processing system according to the present invention.

For convenience, in this embodiment, the data width is described as 32 bits (or 4 bytes).

The store-in cache of this embodiment is controlled so that pipeline processing can be performed as in the prior art. Procedures for the data state of the store-in cache, exchange of data, and the like are out of the scope of the present invention, and a description thereof will be omitted.

A data buffer 1 is a buffer for storing write data from a plurality of processors (four in this embodiment) to a cache, and is controlled by a FIFO. The WBP (Write Byte Position) buffer 2 is a buffer that stores a WBP corresponding to each entry of the data buffer 1 and is controlled in the same manner as the data buffer 1. Here, the WBP is 4-bit information indicating which byte of the data 4 bytes stored in the data buffer 1 is to be written. The selector 4 is a selector for selecting one of the four outputs of the data buffer 1 and the cache registration data when a cache miss occurs. The write data register 5
The output data of the selector 4, which is write data to the cache, is stored. The parity check circuit 3
It exists for each of the four outputs of the buffer 2 and performs a parity check on the output of the WBP buffer. The selector 6 is controlled similarly to the selector 4, and selects the WBP corresponding to the data. The WBP register 7 stores an output of the selector 6, which is a WBP corresponding to the write data register 5. The selector 8 is a selector that selects four outputs of the parity check circuit 3. Control is performed in the same manner as the selectors 4 and 6. The error flag register 9 stores the output of the selector 8. The merge register 10 has an ECC
(Error Correcting Code) The output of the correction circuit 18 is stored. The parity check circuits 11, 12, and 13 perform parity checks on the outputs of the write data register 5, the WBP register 7, and the merge register 10, respectively. The merge circuit 14 merges the outputs of the write data register 5 and the merge register 10 in byte units according to the information of the WBP register 7. The ECC generation circuit 15 generates ECC for 1-bit error correction and 2-bit error detection from the 4-byte data output from the merge circuit 14. The cache memory 16 stores the output of the ECC generation circuit 15 in the entry indicated by the address register 20 on the signal line 20.
This is a RAM to be written when 0 becomes "1".

The read data register 17 stores the contents of the entry of the cache memory 16 indicated by the address register 20. The ECC correction circuit 18 checks the output of the read data register 17 by ECC, corrects a 1-bit error if it is detected, correctly assigns parity to the corrected data, and detects a 2-bit error. If detected, data is output such that a parity error occurs. The reply data register 19 stores the output of the ECC correction circuit 18 and returns cache read data to each processor. The address register 20 stores the address of a read / write entry in the cache memory 16. The WE (Write Enable) register 21 becomes "1" when the request from each processor is "write".

A plurality of the same store-in caches of this embodiment are connected by signal lines 201 and 202.
Data can be exchanged with each other (for example, connected by a bus, not shown).

Next, the operation of the store-in-cache failure processing system of the embodiment will be described with reference to FIG.

It is assumed that a certain processor issues a request to write certain data to the store-in cache (write request). At this time, if a parity error is detected by the parity check circuit 3 when reading the WBP buffer 2, the circuit 1
00 stores a WBP of “0” in all four bits.
At the same time, “1” is set in the error flag register 9.
Is stored. The output of the error flag register 9 is
It is passed to the subsequent stage of the pipeline, and returns an error report during a write operation (hereinafter referred to as an error reply (write)) to the requesting processor. The processing when the error reply (write) is received is left to the processor (for example, the processor is stopped). By performing such processing, even if the WBP attempts to write data in which a parity error has occurred, the output of the circuit 101 becomes "0" and the WE of the cache memory 16 is not activated because it is not activated. Never.
Therefore, there is no need to stop the system. However, when a parity error of WBP is detected by the parity check circuit 12, the system is stopped as in the related art.

When a parity error is detected by the parity check circuit 11 when write data is stored in the write data register 5 in response to a write request from a certain processor, the output of the parity check circuit 11 is output to a pipe. It is passed to the latter stage of the line and returns an error reply (write) to the requesting processor. At this time, path
The output of the check circuit 11 is input to the circuit 103.
It is, with respect to circuit 103 ECC producing formation circuit 15, ECC2
Instructs ECC to generate bit errors
You. As a result, the cache memory 16 has a 2-bit error.
Data is stored in the
The processing when an error reply (write) is received is left to the processor, and the system is not stopped.

The merge register 10 operates when four bytes stored in one entry of the cache memory 16 are written to a part of the four bytes (hereinafter, referred to as partial write).

At the time of a partial write request from a certain processor, four bytes of the corresponding entry of the cache memory 16 are read once and stored in the merge register 10, and the merge data 14 is written by the merge circuit 14 in accordance with the WBP of the WBP register 7. 5 is merged in byte units and stored again in the same entry. At this time, if a parity error of the merge register 10 is detected by the parity check circuit 13, the output of the parity check circuit 13 is input to the circuit 103, and the circuit 103 sends an ECC 2-bit error to the ECC generation circuit 15. Instruct to generate ECC. As a result, data is stored in the cache memory 16 with a 2-bit error.

The output of the parity check circuit 13 is passed to the subsequent stage of the pipeline, and returns an error reply (write) to the requesting processor. The processing when an error reply is received is left to the processor, and the system is not stopped. Also, the cache memory 16
The handling of the 2-bit error data stored in the ECC is left to the processor that has read the data (it looks like parity error data to the processor by passing through the ECC correction circuit 18). In the case where another store-in cache reads the 2-bit error data from the store-in cache of this embodiment, the store-in cache of this embodiment stores the cache registration data from the write data register 5 into the cache memory 16. Is the same as the operation of writing to. In other words, in another store-in cache, the data of the parity error is stored in the write data register 5, so that the parity check circuit 1
At 1, a parity error is detected. Since the output of the parity check circuit 11 is input to the circuit 103 and the cache registration operation is being performed, the circuit 103 instructs the ECC generation circuit 15 to generate an ECC that causes an ECC 2-bit error. As a result, data is stored in the cache memory 16 of another store-in cache with a 2-bit error.

The address register 20 stores a read / write address from the processor. When a parity error is detected by the parity check circuit 22 at the time of a read request from a certain processor, the output of the parity check circuit 22 is passed to the subsequent stage of the pipeline, and an error reply (read) is returned to the requesting processor. The processing when an error reply is received is left to the processor, and the system is not stopped. When a parity error is detected by the parity check circuit 22 at the time of a write request from a certain processor,
The output of the parity check circuit 22 is input to the circuit 102, and the circuit 102 masks the WE signal generated by the circuit 101 to "0". The output of the parity check circuit 22 is passed to the subsequent stage of the pipeline, and an error reply (write) is returned to the requesting processor. The processing when an error reply is received is left to the processor. As a result, there is no possibility of illegally writing to the cache memory 16, so that the system is not stopped.

The number of processors, the number of store-in caches, and the width of the data address can be realized in other than this embodiment in the same manner as described above.

[0020]

As described above, in the store-in-cache failure processing system of the present invention, even if a failure due to a hardware failure is detected during the processing of a read / write request from a processor, the possibility of system suspension may occur. And the operating rate of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a store-in-cache failure processing system according to the present invention.

[Explanation of symbols]

 1 Data buffer 2 WBP buffer 3, 11, 12, 13, 22 Parity check circuit 4, 6, 8 Selector 5 Write data register 7 WBP register 9 Error flag register 10 Merge register 14 Merge circuit 15 ECC generation circuit 16 Cache memory 17 Read Data register 18 ECC correction circuit 19 Reply data register 20 Address register 21 WE register 100-103 circuit 200-202 Signal line

Claims (1)

(57) [Claims] 1. A failure handling system for a store-in cache of a shared memory type multiprocessor system,
When the WBP is read from a buffer holding data (WBP) indicating the byte position of the data to be written to the cache, the parity error of the WBP is detected. When the parity error is detected, the value of the WBP is set to “0”. Value, and when no parity error is detected,
Mask means for outputting the value of the read WBP, first parity check means for parity-checking the output of the write data register holding the data to be written to the cache, and holding the data once read from the cache. A second parity check unit for performing a parity check on an output of the merge register, and an output of the first parity check, an output of the second parity check, and a signal indicating that a cache registration operation is being performed. Instruction means for instructing a code for 1-bit error correction / 2-bit error detection to be written to the cache to appear as a 2-bit error, and 1-bit error correction / 2-bit error detection for the data to be written to the cache And generates a code for the Means for processing the data so as to appear as a two-bit error, and when the data read from the cache has a one-bit error, corrects the data, adds correct parity, and corrects the two-bit error. If it occurs, a parity providing means for providing a parity so as to generate a parity error; a third parity checking means for performing a parity check on an output of an address register indicating an entry to be read / written in the cache; from the signal for instructing the timing of writing to the output and said cache of third parity check means, and inhibition means for inhibiting a write instruction to the cache, before held in the register is selected by the selector
4th parity check of the output from the mask means
Parity check means , wherein the first, second, and
A request for the error result of the third parity check means
Informs the requester and leaves it to the requester's processing,
The error result of the checker is
Fault processing system of store-in cache, wherein that you use as stem stop.