JPS5616983A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5616983A
JPS5616983A JP9209479A JP9209479A JPS5616983A JP S5616983 A JPS5616983 A JP S5616983A JP 9209479 A JP9209479 A JP 9209479A JP 9209479 A JP9209479 A JP 9209479A JP S5616983 A JPS5616983 A JP S5616983A
Authority
JP
Japan
Prior art keywords
information
bit
error
buffer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9209479A
Other languages
Japanese (ja)
Inventor
Minoru Etsuno
Akira Hattori
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9209479A priority Critical patent/JPS5616983A/en
Publication of JPS5616983A publication Critical patent/JPS5616983A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the management of buffer memroy, by compulsively introducing errors in the stored information written in the buffer memory, when errors are present in the data read out from the main memory unit.
CONSTITUTION: In the data transfer from the main memory unit M.MET to the buffer mrmory 2, the data section of the information 1 is shared into a given number of bytes at the information 5, and the parity bit P is produced with the parity producing circuits 6-0W6-7 based on the byte data shared to form one byte's share. Further, the syndrome is produced 7 based on the information 1 and error is judged 8. Further, in case of one-bit error, the output of the circuit 8 makes bit-inversion for an arbitrary one bit in the information 5 compulsively to produce the information 3 in error correction. In case of two-bit error, the error which can all invert the partity bit in the information 5 with the output of the circuit 9, is introduced to constitute the information 3.
COPYRIGHT: (C)1981,JPO&Japio
JP9209479A 1979-07-19 1979-07-19 Data processing system Pending JPS5616983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9209479A JPS5616983A (en) 1979-07-19 1979-07-19 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9209479A JPS5616983A (en) 1979-07-19 1979-07-19 Data processing system

Publications (1)

Publication Number Publication Date
JPS5616983A true JPS5616983A (en) 1981-02-18

Family

ID=14044852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9209479A Pending JPS5616983A (en) 1979-07-19 1979-07-19 Data processing system

Country Status (1)

Country Link
JP (1) JPS5616983A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08286977A (en) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk System for processing fault of in-store cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08286977A (en) * 1995-04-14 1996-11-01 Kofu Nippon Denki Kk System for processing fault of in-store cache

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