JPS5619598A - Memory error control unit - Google Patents

Memory error control unit

Info

Publication number
JPS5619598A
JPS5619598A JP9451779A JP9451779A JPS5619598A JP S5619598 A JPS5619598 A JP S5619598A JP 9451779 A JP9451779 A JP 9451779A JP 9451779 A JP9451779 A JP 9451779A JP S5619598 A JPS5619598 A JP S5619598A
Authority
JP
Japan
Prior art keywords
section
address
data
error
incorrigible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9451779A
Other languages
Japanese (ja)
Inventor
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9451779A priority Critical patent/JPS5619598A/en
Publication of JPS5619598A publication Critical patent/JPS5619598A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To enable to use the memory unit continuously, by providing the substitute memory section consisting of the data section, address section and effective indicating section.
CONSTITUTION: The substitute memory section 7 provides the effective indicating section 8, address section 9 and data section 10. Further, when the error correction circuit 3 generates the incorrigible error production indicating signal ER such as 2-bit error, the set signal is given to the indication section 8 and the address section 9, and the address causing the incorrigible error, that is, the content of the address register 2 is set to the address section 9. Further, the incorrigible data is reproduced and written in the data section 10. Next, every time when the address information is set to the register 2, comparison by the comparison circuit 11 is made, and if in agreement, the content of the data 10 is fed to the correction circuit 3. Thus, the memory unit can continuously be used.
COPYRIGHT: (C)1981,JPO&Japio
JP9451779A 1979-07-25 1979-07-25 Memory error control unit Pending JPS5619598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9451779A JPS5619598A (en) 1979-07-25 1979-07-25 Memory error control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9451779A JPS5619598A (en) 1979-07-25 1979-07-25 Memory error control unit

Publications (1)

Publication Number Publication Date
JPS5619598A true JPS5619598A (en) 1981-02-24

Family

ID=14112511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9451779A Pending JPS5619598A (en) 1979-07-25 1979-07-25 Memory error control unit

Country Status (1)

Country Link
JP (1) JPS5619598A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131147A (en) * 1984-11-30 1986-06-18 Fujitsu Ltd Storage device
US6411558B1 (en) 1998-12-17 2002-06-25 Nec Corporation Semiconductor device for compensating a failure therein
JP2009181439A (en) * 2008-01-31 2009-08-13 Toshiba Corp Memory system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131147A (en) * 1984-11-30 1986-06-18 Fujitsu Ltd Storage device
JPH0376506B2 (en) * 1984-11-30 1991-12-05 Fujitsu Ltd
US6411558B1 (en) 1998-12-17 2002-06-25 Nec Corporation Semiconductor device for compensating a failure therein
JP2009181439A (en) * 2008-01-31 2009-08-13 Toshiba Corp Memory system

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