JPS5619596A - Parity error processing system - Google Patents

Parity error processing system

Info

Publication number
JPS5619596A
JPS5619596A JP9355479A JP9355479A JPS5619596A JP S5619596 A JPS5619596 A JP S5619596A JP 9355479 A JP9355479 A JP 9355479A JP 9355479 A JP9355479 A JP 9355479A JP S5619596 A JPS5619596 A JP S5619596A
Authority
JP
Japan
Prior art keywords
parity error
block
processing circuit
parity
importance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9355479A
Other languages
Japanese (ja)
Inventor
Motoharu Asano
Kanko Yuki
Hideo Matsuda
Kenichi Hanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9355479A priority Critical patent/JPS5619596A/en
Publication of JPS5619596A publication Critical patent/JPS5619596A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To perform different processing according to the importance of data, by making different report to the processor depending on the memory block at the generation of parity error.
CONSTITUTION: When the parity addition and check circuit 3 detects the parity error, the information is reported to the parity error processing circuit 5. Further, the address decoder 7 identifies the address belonging to the block 8 in the main memory 2 or the address belonging to the block 9 and the identified signal is fed to the processing circuit 5. Next, the processing circuit 5 receiving the information feeds the different report based on the difference of the block in which parity error is taken place, to the status display register 4. Further, the processor 1 can make processing different depending on the importance of the stored data, based on the content of the register 4.
COPYRIGHT: (C)1981,JPO&Japio
JP9355479A 1979-07-23 1979-07-23 Parity error processing system Pending JPS5619596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9355479A JPS5619596A (en) 1979-07-23 1979-07-23 Parity error processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9355479A JPS5619596A (en) 1979-07-23 1979-07-23 Parity error processing system

Publications (1)

Publication Number Publication Date
JPS5619596A true JPS5619596A (en) 1981-02-24

Family

ID=14085463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9355479A Pending JPS5619596A (en) 1979-07-23 1979-07-23 Parity error processing system

Country Status (1)

Country Link
JP (1) JPS5619596A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59216255A (en) * 1983-05-25 1984-12-06 Fujitsu Ltd Error detecting system of interruption stack area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59216255A (en) * 1983-05-25 1984-12-06 Fujitsu Ltd Error detecting system of interruption stack area

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