JPS5611696A - Error detection circuit - Google Patents

Error detection circuit

Info

Publication number
JPS5611696A
JPS5611696A JP8438679A JP8438679A JPS5611696A JP S5611696 A JPS5611696 A JP S5611696A JP 8438679 A JP8438679 A JP 8438679A JP 8438679 A JP8438679 A JP 8438679A JP S5611696 A JPS5611696 A JP S5611696A
Authority
JP
Japan
Prior art keywords
circuit
readout
memory
output
inhibition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8438679A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nagayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8438679A priority Critical patent/JPS5611696A/en
Publication of JPS5611696A publication Critical patent/JPS5611696A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable to detect failure of readout inhibition circuit, by the parity check for the output of read only memory and that of the readout inhibition circuit controlling this memory.
CONSTITUTION: When the readout inhibition circuit 101 applies the readout indicating low level signal to the read-only memory 100, the content of the memory 100 according to the address is read out. Further, the parity being an odd number for the high level output stored in advance on the output lines 1W4 of the memory 100 is read out and fed to the parity check circuit 102. On the other hand, the readout indicating low level signal is fed to the circuit 102 from the circuit 101 to confirm that the even number output line 8 of the circuit 102 is at low level and the readout is correctly made. At inhibition of readout, the high level output of the output lines 1W4 of the circuit 100 and the readout inhibition high level output from the circuit 101 are fed to the circuit 102 to confirm normal operation of the memory 100. In this case, to confirm the operation, the output information of the readout inhibition circuit is given, enabling failure detection of the readout inhibition circuit also.
COPYRIGHT: (C)1981,JPO&Japio
JP8438679A 1979-07-05 1979-07-05 Error detection circuit Pending JPS5611696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8438679A JPS5611696A (en) 1979-07-05 1979-07-05 Error detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8438679A JPS5611696A (en) 1979-07-05 1979-07-05 Error detection circuit

Publications (1)

Publication Number Publication Date
JPS5611696A true JPS5611696A (en) 1981-02-05

Family

ID=13829115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8438679A Pending JPS5611696A (en) 1979-07-05 1979-07-05 Error detection circuit

Country Status (1)

Country Link
JP (1) JPS5611696A (en)

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