JPS5619597A - Diagnostic and processing system for memory unit - Google Patents

Diagnostic and processing system for memory unit

Info

Publication number
JPS5619597A
JPS5619597A JP9451379A JP9451379A JPS5619597A JP S5619597 A JPS5619597 A JP S5619597A JP 9451379 A JP9451379 A JP 9451379A JP 9451379 A JP9451379 A JP 9451379A JP S5619597 A JPS5619597 A JP S5619597A
Authority
JP
Japan
Prior art keywords
register
error
memory
information
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9451379A
Other languages
Japanese (ja)
Other versions
JPS607821B2 (en
Inventor
Masaaki Inao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54094513A priority Critical patent/JPS607821B2/en
Publication of JPS5619597A publication Critical patent/JPS5619597A/en
Publication of JPS607821B2 publication Critical patent/JPS607821B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enable to discriminate the failed bit location of the memory mounted on the package, by comparison of correct data read out from the memory in other nondefective state, in bit correspondence.
CONSTITUTION: When an error is detected at the parity error detection circuit 13, the error data is stored to the register 10, the address information is register 11 and the access control information is to the register 12 respectively. Further, the error byte location information is stored in the register 14 and the main memory unit 16 being nondefective memory is accessed with the retrial control 15 and correct data are set to the register 9. Next, each information is respectively fed to the scan out data storage section and the content of the register 9 and that of the register 10 are compared at the bit correspondence comparison section 19. Thus, the failed bit location can be judged.
COPYRIGHT: (C)1981,JPO&Japio
JP54094513A 1979-07-25 1979-07-25 Storage device diagnostic processing method Expired JPS607821B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54094513A JPS607821B2 (en) 1979-07-25 1979-07-25 Storage device diagnostic processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54094513A JPS607821B2 (en) 1979-07-25 1979-07-25 Storage device diagnostic processing method

Publications (2)

Publication Number Publication Date
JPS5619597A true JPS5619597A (en) 1981-02-24
JPS607821B2 JPS607821B2 (en) 1985-02-27

Family

ID=14112397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54094513A Expired JPS607821B2 (en) 1979-07-25 1979-07-25 Storage device diagnostic processing method

Country Status (1)

Country Link
JP (1) JPS607821B2 (en)

Also Published As

Publication number Publication date
JPS607821B2 (en) 1985-02-27

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