JPS55117799A - Fault processing system - Google Patents

Fault processing system

Info

Publication number
JPS55117799A
JPS55117799A JP2293779A JP2293779A JPS55117799A JP S55117799 A JPS55117799 A JP S55117799A JP 2293779 A JP2293779 A JP 2293779A JP 2293779 A JP2293779 A JP 2293779A JP S55117799 A JPS55117799 A JP S55117799A
Authority
JP
Japan
Prior art keywords
contents
memory unit
read
address
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2293779A
Other languages
Japanese (ja)
Other versions
JPS5918799B2 (en
Inventor
Mamoru Hinai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54022937A priority Critical patent/JPS5918799B2/en
Publication of JPS55117799A publication Critical patent/JPS55117799A/en
Publication of JPS5918799B2 publication Critical patent/JPS5918799B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it easy to point out a defective bit on the basis of byte parity when a fault occurs, even in case that a buffer memory unit and data matching circuit are increased in operation speed, by providing a memory unit with an address stack.
CONSTITUTION: A control signal for error occurrence suppresses storage in units following address stacks 9 and 10, which is reported to fault processor 1. Processor 1, having the method of reading address stacks 9-2 and 10-2, validates the contents of stack 9-2 to read the contents of buffer memory unit 11, and then validates the contents of stack 10-2 to read the contents of main memory unit 4, and after the logout address of a computer system is validated, data from units 11 and 4 are written in the logout area of unit 4. The contents of this logout area are read out and then compared with read data from units 11 and 4, so that a defective bit can be pointed out.
COPYRIGHT: (C)1980,JPO&Japio
JP54022937A 1979-02-28 1979-02-28 Failure handling method Expired JPS5918799B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54022937A JPS5918799B2 (en) 1979-02-28 1979-02-28 Failure handling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54022937A JPS5918799B2 (en) 1979-02-28 1979-02-28 Failure handling method

Publications (2)

Publication Number Publication Date
JPS55117799A true JPS55117799A (en) 1980-09-10
JPS5918799B2 JPS5918799B2 (en) 1984-04-28

Family

ID=12096539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54022937A Expired JPS5918799B2 (en) 1979-02-28 1979-02-28 Failure handling method

Country Status (1)

Country Link
JP (1) JPS5918799B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0710557U (en) * 1985-04-18 1995-02-14 ザ トリングトン カムパニー Hermetically sealed bearings

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0710557U (en) * 1985-04-18 1995-02-14 ザ トリングトン カムパニー Hermetically sealed bearings

Also Published As

Publication number Publication date
JPS5918799B2 (en) 1984-04-28

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