JPS5687153A - Controller for auxiliary memory - Google Patents

Controller for auxiliary memory

Info

Publication number
JPS5687153A
JPS5687153A JP16415679A JP16415679A JPS5687153A JP S5687153 A JPS5687153 A JP S5687153A JP 16415679 A JP16415679 A JP 16415679A JP 16415679 A JP16415679 A JP 16415679A JP S5687153 A JPS5687153 A JP S5687153A
Authority
JP
Japan
Prior art keywords
address
sector
data
designating
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16415679A
Other languages
Japanese (ja)
Inventor
Tadao Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16415679A priority Critical patent/JPS5687153A/en
Publication of JPS5687153A publication Critical patent/JPS5687153A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To pick up a defective program and to make easy debugging by detecting the destruction caused through the processing of program, when undesirable data is written in to the specific address of specific sector.
CONSTITUTION: The information such as the sector address designation signal 20 designating the sector fed from the computer, word address designation signal 25 designating the word address in the sector, and data designation signal 31 designating the key of address, in input and stored in the sector address designation register 1, word address designation register 4, and data designation register 8. Further, the address information 22, 27 changed in timing with the access and transfer of memory, is formed with the sector address counter 3, word address counter 6, and selection and word address increment signals 23, 28. Further, the designated data 32 and the transfer data 33 are compared at the data comparison circuit 9, the result is fed to the logic circuit, the interruption signal 39 is output, and the defective program is picked up.
COPYRIGHT: (C)1981,JPO&Japio
JP16415679A 1979-12-19 1979-12-19 Controller for auxiliary memory Pending JPS5687153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16415679A JPS5687153A (en) 1979-12-19 1979-12-19 Controller for auxiliary memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16415679A JPS5687153A (en) 1979-12-19 1979-12-19 Controller for auxiliary memory

Publications (1)

Publication Number Publication Date
JPS5687153A true JPS5687153A (en) 1981-07-15

Family

ID=15787797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16415679A Pending JPS5687153A (en) 1979-12-19 1979-12-19 Controller for auxiliary memory

Country Status (1)

Country Link
JP (1) JPS5687153A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214989A (en) * 1988-02-24 1989-08-29 Oki Electric Ind Co Ltd Information recording and processing device
JPH01273169A (en) * 1988-04-26 1989-11-01 Oki Electric Ind Co Ltd Information recording processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214989A (en) * 1988-02-24 1989-08-29 Oki Electric Ind Co Ltd Information recording and processing device
JPH01273169A (en) * 1988-04-26 1989-11-01 Oki Electric Ind Co Ltd Information recording processor

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