JPS55117780A - Buffer memory unit - Google Patents

Buffer memory unit

Info

Publication number
JPS55117780A
JPS55117780A JP2528079A JP2528079A JPS55117780A JP S55117780 A JPS55117780 A JP S55117780A JP 2528079 A JP2528079 A JP 2528079A JP 2528079 A JP2528079 A JP 2528079A JP S55117780 A JPS55117780 A JP S55117780A
Authority
JP
Japan
Prior art keywords
access
block
cash
giving
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2528079A
Other languages
Japanese (ja)
Inventor
Masanobu Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2528079A priority Critical patent/JPS55117780A/en
Publication of JPS55117780A publication Critical patent/JPS55117780A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enable high-speed access by registering new data in a block with the highest eviction priority according to the contents of a LRU memory in case of a cash miss bit, and then by giving the block the lowest eviction priority.
CONSTITUTION: Byte address information from instruction processing part 30 is stored in register 10 of buffer memory 60, and access to address array 11 is attained to input address information and effective bit information of four blocks from array 11 to corresponding comparator circuits 12W15. When any one of four blocks disagrees (cash miss bit), access to main memory unit 50 is started. In a cash access cycle, LRU memory 20 is updated by giving a write control signal and a block where a coincidence is obtained through comparison is given the lowest priority being considered to be accessed most newly.
COPYRIGHT: (C)1980,JPO&Japio
JP2528079A 1979-03-05 1979-03-05 Buffer memory unit Pending JPS55117780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2528079A JPS55117780A (en) 1979-03-05 1979-03-05 Buffer memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2528079A JPS55117780A (en) 1979-03-05 1979-03-05 Buffer memory unit

Publications (1)

Publication Number Publication Date
JPS55117780A true JPS55117780A (en) 1980-09-10

Family

ID=12161603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2528079A Pending JPS55117780A (en) 1979-03-05 1979-03-05 Buffer memory unit

Country Status (1)

Country Link
JP (1) JPS55117780A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162956A (en) * 1987-12-18 1989-06-27 Nec Ic Microcomput Syst Ltd Sequence storage circuit
JPH0354372B2 (en) * 1982-09-22 1991-08-20

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354372B2 (en) * 1982-09-22 1991-08-20
JPH01162956A (en) * 1987-12-18 1989-06-27 Nec Ic Microcomput Syst Ltd Sequence storage circuit

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