JPS57172582A - Cash memory control method - Google Patents

Cash memory control method

Info

Publication number
JPS57172582A
JPS57172582A JP56055667A JP5566781A JPS57172582A JP S57172582 A JPS57172582 A JP S57172582A JP 56055667 A JP56055667 A JP 56055667A JP 5566781 A JP5566781 A JP 5566781A JP S57172582 A JPS57172582 A JP S57172582A
Authority
JP
Japan
Prior art keywords
register
address
processor
bit
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56055667A
Other languages
Japanese (ja)
Other versions
JPH0127455B2 (en
Inventor
Tetsuya Kawakami
Tadaaki Bando
Yasushi Fukunaga
Yoshinari Hiraoka
Hidekazu Matsumoto
Takeshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP56055667A priority Critical patent/JPS57172582A/en
Publication of JPS57172582A publication Critical patent/JPS57172582A/en
Publication of JPH0127455B2 publication Critical patent/JPH0127455B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To improve the number of hits by holding coincidence between data of a cash memory and that of a common-use memory without deteriorating the processing performance of processors even when the number of processors increases. CONSTITUTION:During write access from a processor, an address is latched in a processor address register 101, write data in a write data register 121, and an access key in an access key register 103. In a time t2 shown by P1 on the line of a directory 80 and an significant bit 90, the directory 80 and significant bit 90 including a protection bit as well as the address are accessed at the column bit part of the processor address register 101, and the read address is compared by a comparator 112 with the load bit part of the processor address register 101 sent through a selector 107 to check their coincidence.
JP56055667A 1981-04-15 1981-04-15 Cash memory control method Granted JPS57172582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055667A JPS57172582A (en) 1981-04-15 1981-04-15 Cash memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055667A JPS57172582A (en) 1981-04-15 1981-04-15 Cash memory control method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2115879A Division JPH0387949A (en) 1990-05-07 1990-05-07 Cache memory controller

Publications (2)

Publication Number Publication Date
JPS57172582A true JPS57172582A (en) 1982-10-23
JPH0127455B2 JPH0127455B2 (en) 1989-05-29

Family

ID=13005203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055667A Granted JPS57172582A (en) 1981-04-15 1981-04-15 Cash memory control method

Country Status (1)

Country Link
JP (1) JPS57172582A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63253448A (en) * 1987-04-10 1988-10-20 Hitachi Ltd Multi-computer device
JPH028946A (en) * 1988-06-28 1990-01-12 Mitsubishi Electric Corp Cache memory control system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51148334A (en) * 1975-06-16 1976-12-20 Hitachi Ltd Buffer memory control method
JPS5464944A (en) * 1977-11-02 1979-05-25 Fujitsu Ltd Buffer invalidating system for multi-cpu system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51148334A (en) * 1975-06-16 1976-12-20 Hitachi Ltd Buffer memory control method
JPS5464944A (en) * 1977-11-02 1979-05-25 Fujitsu Ltd Buffer invalidating system for multi-cpu system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63253448A (en) * 1987-04-10 1988-10-20 Hitachi Ltd Multi-computer device
JPH0511337B2 (en) * 1987-04-10 1993-02-15 Hitachi Ltd
JPH028946A (en) * 1988-06-28 1990-01-12 Mitsubishi Electric Corp Cache memory control system

Also Published As

Publication number Publication date
JPH0127455B2 (en) 1989-05-29

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