JPH0354372B2 - - Google Patents

Description

Claim 1: An apparatus for increasing the storage capacity of a data processing system, the system comprising: a main memory 102; a cache memory system 100; addressing the cache memory system and the main memory. means 101; the cache memory system 100 includes: a plurality of cache memories 107-109, each containing word groups that also exist redundantly in main memory 102; means 104-106 for determining whether the stored first word is also stored in one of the cache memories; Determination means 104-10
a control circuit 1 for storing a first word in a first cache memory in response to an instruction from 6;
03; wherein the first memory transfers the most recently used previously stored word to the second cache memory in response to receiving the first word. A device that increases the storage capacity of a processing system. 2. A method for increasing storage capacity of a data processing system, the system comprising: a main memory 102; a cache memory system 100; a cache memory system and a main memory system 100;
means 101 for addressing memory; the method includes: ordering words stored in cache memory system 100 according to relative time of use; and determining whether the word is stored in one of the cache memories 107-109 forming the cache memory system 100, storing the word in the first cache memory, and storing the word in the least recently used cache memory. A method for increasing the storage capacity of a data processing system comprising the steps of causing a transfer of stored words from a first memory to a second cache memory. 3. In a data processing system, the system comprises: processor means for generating main memory address signals; main memory having a plurality of memory locations for storing main memory words; cache control means; having a plurality of memory locations for storing main memory addresses and corresponding cache data words, and having a main memory address signal inconsistent with all main memory addresses stored therein; first and second cache memories responsive to generating and transmitting a mismatch signal to the cache control means; the cache control means generating the mismatch signal simultaneously by the first and second cache memories; in response to generating and transmitting a first control signal to the main memory and the first and second cache memories; the main memory generating the first control signal and the mismatched main control signal; transmitting the main memory word to the first cache memory in response to the memory address signal; the first cache memory transmitting the most recently used cache data word in response to the first control signal; transmitting the word and corresponding stored main memory address to a second cache memory and storing the transmitted main memory word and main memory address signal; A data processing system for storing a cache data word and a corresponding main memory address transmitted in response to a first control signal. 4. The data processing system of claim 3, wherein the second cache memory further comprises a coherent memory having a plurality of memory locations for storing main addresses and a plurality of memory locations for storing cache data words. a data memory having memory locations for the data memory; the aligned memory responsive to aligned main memory address signals; memory·
generating and transmitting an address, and generating and transmitting a mismatch signal in response to the mismatched main memory address signal; - A data processing system characterized by accessing and transmitting data words. TECHNICAL FIELD The present invention relates to computer systems, and more particularly to systems that use a cache memory in which the location for storing new information is the location of the lowest priority word in the cache memory. BACKGROUND OF THE INVENTION Modern computer systems use processors capable of operating at high speeds that a single large capacity memory cannot keep up with. For this reason, small amounts of high-speed cache memory are typically used in conjunction with large amounts of main memory to improve program execution speed. The cache memory stores a limited number of instructions or data words, and each memory read operation examines the cache memory for the presence of information. If the information is present, it is read from cache memory. If the information does not exist in cache memory, it is read from main memory. If information has to be read from main memory, the new information must replace the existing information in cache memory. Suitable locations for storing new information in cache memory include several widely used replacement algorithms (e.g., random replacement,
(replace most previously used, etc.). It is generally believed that the algorithm that replaces the one most previously used is the most efficient algorithm. However, determining which location contains the least recently used word has proven difficult to accomplish in a time-consuming and economically competitive manner. SUMMARY OF THE INVENTION A cache memory system according to the present invention is divided into several sections containing groups of data words. Each section has a priority circuit that maintains a relative priority determined according to the time the word stored therein was last used. Upon receiving a main memory word that must be inserted into cache memory, the time required to update the cache memory is such that the word is stored in one section while the lowest priority word from a higher priority section to a lower priority section.
It can be reduced by moving to the section. In one embodiment of the invention, a data processing system comprises a processor that requests data words by generating main memory address signals, and a main memory and cache memory system. The cache memory system includes a cache control circuit and first and second cache memories. A cache memory system having one or more cache memories allows the system to be expanded in the field. Furthermore, each cache memory can be implemented as a single LSI circuit. Each cache memory contains a cache data word (which is a duplicate of the word stored in main memory)
and the corresponding main memory address. A processor requests a data word by transmitting a main memory address signal. The contents of the first and second cache memories are examined to determine whether the requested word is present therein. If the cache memory contains the desired word, the cache memory transmits a match signal to the cache control circuit. If the desired word is not included, the cache memory transmits a mismatch signal. When the cache control circuit receives mismatch signals from both cache memories, it causes two operations to occur. During the first operating period, the main
The memory is responsive to main memory address signals to access and transmit desired main memory words to the processor and first cache memory. Also during this first period of operation, the first cache memory accesses the lowest priority cache data word having the associated main memory address stored;
Transfer the word to a second cache memory. During a second period of operation, the first cache memory stores the accessed main memory word and main memory address signal in the previously accessed first cache memory location; cache memory stores the lowest priority cache data word from the first cache memory and the stored main memory address from the first accessed second cache memory.
Stored in cache memory location. The cache control means causes two operations to be performed in the cache memory in response to a mismatch signal from the first cache memory and a match signal from the second cache memory. During a first period of operation, the first cache memory accesses and transmits the lowest priority cache data word and associated main memory address to the second cache memory, and transfers the lowest priority cache data word and associated main memory address to the second cache memory. - The memory transmits the cache data word associated with the aligned stored memory address to the first cache memory and processor. During the second period of operation, the first cache memory transfers cache data words and addresses from the second cache memory to the previously lowest priority cache data words and memory addresses. stored in the memory location previously used. Also during the second period of operation, the second cache memory stores addresses associated with cache data words transmitted from the first cache memory. Each cache memory includes alignment memory and data memory. Coherent memory stores main memory addresses and stores data.
The memory stores cache data words. The matched memory compares each set of main memory address signals sent by the processor;
Indicate alignment or inconsistency. When alignment occurs,
The matching memory transmits the address to the data memory, thereby accessing and transmitting the desired cache data word. Content addressable memory can be used to implement coherent memory. Additionally, each cache memory has a priority circuit that maintains the priority of each cache data word as to when it is accessed within the first cache memory. The priorities maintained by the priority circuit are a history of the times of use of cache data words. The lowest priority cache data word is the most recently used word. The cache memory system stores the cache data words in the cache memory system such that the first section contains words that have a higher priority than the words stored in the second section. accessed and updated. Processor
When accessing a word, each section is checked to see if the desired word is contained within it. If the desired word is not contained in either section, main memory is accessed and the desired word is transmitted to the processor and the first section. the accessed main memory word is used to replace the lowest priority cache data word of the first section;
The highest priority cache data
Becomes a word. The second lowest priority word then becomes the lowest priority cache data word. Prior to that, the lowest priority cache data
The word is transmitted to the second section where the data word replaces the lowest priority word in the second section and becomes the highest priority word in the section. At this time, the word with the second lowest priority in the second section becomes the word with the lowest priority. If the requested word is found to be in the second section, the word from the second section is transmitted to the processor and placed in the first section as the highest priority word in the first section. be remembered. The lowest priority word of the first section is then transferred to the second section, where it becomes the highest priority word of the second section. The word with the lowest priority is the word most recently used, and the word with the highest priority is the word most recently used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the data processing system of the present invention, and FIGS. 2 and 3 are the LRU circuit 10 of FIG.
Figure 4 shows the LRU of Figure 1 in more detail.
FIG. 5 is a diagram showing the content addressable memory of circuit 104 in more detail. FIG. 5 is a table showing an example of the operation of the priority circuit of FIG. DETAILED DESCRIPTION In the data processing system shown in Figure 1, data and instruction words are
Memory 102 and cache system 100
is stored in the memory location of Processor 101 reads the contents of these memory locations by transmitting addresses over address bus 112 and control signals over control bus 113. Cash system 10
0 is the control sequencer 103, the LRU circuit 104,
105 and 106, cache data memories 107, 108 and 109, and a cache data gate circuit 110.
The LRU circuit and cache data memory are arranged in pairs, each pair forming a cache memory unit. For example, LRU circuit 104
and cache data memory 107 form one cache memory unit. The cache data words stored in cache data memory are divided into groups, with each group containing the cache data words that were last read by processor 101 at the same time.
Contains data words. Each group is stored in one of the cache data memories. For example, the most recently used group of words is stored in cache data memory 107 and the least recently used group of words is stored in cache data memory 109. When processor 101 performs a read, cache data words are transferred between cache data memories to maintain a time history of memory usage. For example, if a word needs to be read from main memory 102, this main memory word occupies the position of the most recently used cache data word in cache data memory 104 and the replaced cache data word occupies the position of the most recently used cache data word in cache data memory 104. - The data word is transferred to cache data memory 108. During a read operation, the address transmitted by processor 101 is sent to LRU circuits 104, 105,
and 106, the addressed word is stored in cache data memory 1.
07, 108, or 109, respectively. For example, if LRU circuit 104 determines that the addressed word is contained in cache data memory 107, circuit 107 transmits the address of this word to cache data memory 107 via cable 131. . In response to this address, cache data memory 107 accesses the desired word and transmits it to cache data gate circuit 110.
From cache data gate circuit 110, the desired data word is transmitted to processor 101 via data bus 111. LRU circuit 10
4 to processor 1 via address bus 112.
If the circuit 104 determines that the address does not match the address transmitted by 01, the control sequencer 103
A "1" signal is transmitted through conductor 114 to indicate that there was a mismatch. Other LRU circuits operate in a similar manner. In addition to checking whether the associated cache data memory has the desired memory word, the LRU circuit maintains the priority of each word in the associated cache data memory. This priority information is automatically updated by the LRU circuitry each time the associated cache data memory is accessed and defines which word in the cache memory is the least recently used word. The operation of the system is further illustrated by three examples described below. The first example assumes that the desired word does not exist in cache system 100 and must be read from main memory 102. If the desired word does not exist in cache system 100, all LRUs
The circuit transmits a "1" signal via matching lines 114, 115 and 116. In response to these signals, the control sequencer 103
and obtain the desired word. Maine·
Since the word read from memory 102 is the most recently used word, it is added into cache data memory 107 and the least recently used word from cache data memory 107 is added to cache data memory 107. - The least recently used word of cache data memory 108 written into data memory 108 is written into cache data memory 109. The most recently used word of cache data memory 109 is no longer present in cache memory 100 upon completion of the operations described above. In a second example of operation of cache memory system 100, the desired word is
Assume that it resides in data memory 107. Since the desired word is in cache data memory 107, main memory 102
There is no need to access or transfer memory words from cache data memory 107 to cache data memory 108. Instead, LRU circuit 104 will simply update the priority information stored within circuit 104 to properly reflect the order of use of memory words in data memory 107. In the third example, assume that the desired memory word resides in data memory 108. In this case, LRU circuit 105 matches the address transmitted to processor 101 via address bus 112, causes data memory 108 to access the desired word, and transmits the word to data gate circuit 110. Ru. Control sequencer 103 then transfers this desired data word to data bus 111 by data gate circuit 110.
The data is transmitted to the processor 101 via the . Since this desired word is the most recently used word, it must be written into data memory 107. The most recently used word of data memory 107 must be written into the memory location previously used by the desired memory word in data memory 108. Although LRU circuit 105 is shown in FIGS. 2 and 3, LRU circuit 106 has a similar configuration. LRU circuit 104 is shown in FIG.
FIG. 2 shows that the address transmitted by processor 101 via address bus 112 is checked to ensure that the desired word is stored in cache data memory 1.
3 shows the circuitry used to determine whether the cache data memory 108 exists in the Showing details of the circuit. When processor 101 reads one word, the processor first reads
Control bus 11 for CAGO signal and clock signal
3 to control sequencer 103, and processor 101 transmits the address via address bus 112. The control sequencer 103 generates a C signal and an S signal in response to these signals,
The signal is routed to the LRU via conductors 122 and 123.
transmitted to the circuit. Data selector 202 selects address bus 1 in response to the C signal on conductor 122.
12 and connect these address bits to conductors 216-2.
23 to the data-in input of content addressable memory (CAM) 201.
CAM contains four words of 8 bits each. The CAM is responsive to the input transmitted via conductor 123 and the address bits received at the data in input and compares these address bits with the contents of each of four internally stored words. When one of the four words matches an address bit, a "1" is transmitted over the associated conductor 212, 213, 214 or 215. If there is no match, “1” is the conductor 23
6 and stored in flip-flop 206 at time T1. If matched, the state of conductors 212-215 is stored in latch 204 by the falling edge of the S signal transmitted through conductor 123. Data selector 205
selects the contents of latch 204, and the contents of the selected latch 204 are applied via conductors 224-227 and then via conductors 228-231 and cable 132 to cache data memory 10.
8. Cash word memory 1
08 accesses the desired word in response to the address transmitted over cable 132 and transmits this word to data gate circuit 110 as described above. Assuming that the desired word has been stored in data memory 108, that word will then be the most recently used word and therefore must be transferred to data memory 107, and will be the most recently used word in data memory 107. The word used is transferred to data memory 108 and the address of this word is written into CAM 201. FIG. 4 shows the circuitry used to check the address transmitted by processor 101 over address bus 112 to determine whether the desired word is present in cache data memory 107. FIG. 3 shows details of the priority circuitry used to track the least recently used word in cache data memory 108. The circuit of FIG. 4 is identical in operation to the circuit of FIG. 2 except that it does not include a data selector similar to data selector 202 of FIG. 2 and includes a priority circuit 444. Priority circuit 444 is the same as the priority circuit described with reference to FIG. A data selector is not required because the circuit of FIG. 4 always uses addresses transmitted over address bus 112. The circuit of FIG. 4 does not require a data selector because it is associated with the most recently used word in cache memory 100 and therefore does not require an address selector like the circuit shown in FIG. This is because there is no need to determine whether to use data from bus 112 or from the LRU circuit with the highest priority. This point will become clearer from the examples given below. To explain the operation of the circuits shown in FIGS. 2 and 4, Example 3, discussed above, will be used. Example 3 provides the operations to be performed when the desired word is present in data memory 108. A more detailed explanation of this example will be provided here, starting with LRU circuit 1.
05 and then discuss the corresponding operation in LRU circuit 104.
Assume that word 1 in data memory 108 and word 2 in data memory 107 are the least recently used words. To perform these different operations, the control sequencer 103
generates a number of timing signals, the most important of which are T0-T4. During period T0, address bits on address bus 112 are selected by data selector 202;
It is used in the CAM 201 to search for a match. These address bits are CAM2
Assuming a match with the contents of word 2 in 01, a "1" is generated on lead 213, but leads 212, 214 and 215 are "0".
This operation is caused by the S signal transmitted to the CAM 201 via the conductor 123 and the CAM 201 via the conductor 122.
201 is executed under the control of the C signal transmitted to 201. The information on conductors 212-215 is stored in latch 204 at the end of the S signal. In addition, the S signal also acts as a clock to clock the matched output terminal of CAM 201 into flip-flop 206. M of the output of flip-flop 206
2 signals are sent to the control sequencer 10 via conductor 115.
3. During period T1, data selector 203 selects the output of latch 204 as an address in response to the M2 signal, which address is transmitted to CAM 201 via conductors 208-211, and data selector 205 responds to the M2 signal. selects the output of latch 204 as the address, which is transmitted to data memory 108 via cable 132. In response to the address on conductors 208-211, CAM 201 reads the contents of the second word, transmits these contents to latch 207, and outputs T1.
At the end of the latch 20, these contents are
It is memorized in 7. Data memory 108 reads the contents of its second word in response to the address transmitted over cable 132. These contents are stored inside the data memory 108,
It is transmitted to data gate circuit 110. During period T1, LRU circuit 104 accesses the address of the most recently used word and transmits the address to LRU circuit 105 via cable 117;
Data memory 107 accesses the most recently used word and transmits that word via cable 140 to data memory 108, as described below. The address from LRU circuit 104 is written into CAM 201 and the corresponding data word is written into data memory 108. During T2 period, data selector 2
03 again selects the output of latch 204 containing the address of word 2 used as the address for CAM 201. The most recently used address word from the LRU circuit is stored in word 2. During the T2 period, the control sequencer 103 transmits the W signal via conductor 124 and the RPL2 signal via conductor 120, thereby transmitting the CAM 20
1 transfers the information present on the data input terminal to word 2
Write inside. At the same time, data memory 1
The 07 most recently used word is written into word 2 of data memory 108. The address is then provided by the output of latch 204 via data selector 205 and cable 132. As described below, the priority circuit shown in FIG.
is updated during T3 to reflect the fact that it is the most recently used word in 5 and not the least recently used word. During T4, flip-flop 206 is reset. Here, Example 3 is explained by referring to FIG.
4 will be described below. During the T0 period, CAM401
A search is carried out. However, since there is no matching, the matching output terminal becomes “0”, and this “0” is the flip
The M1 signal is stored in flop 406 and is not transmitted to control sequencer 103. Since there is no M1 signal during the T1 period,
CAM 401 is addressed by an address from priority circuit 444. This address is connected to conductors 432-435, data selector 40.
3 and conductors 408 to 411 to CAM40.
1 address in terminal. This address bit is the address of the most recently used word of CAM 401 and data memory 107. Also, during the T1 period, data memory 10
7 is data selector 405 and cable 13
1 via the output of priority circuit 444. At the end of T1, the output data of CAM 401 is written into latch 407. The contents of latch 407 are transmitted to LRU circuit 105 via cable 117. During the T2 period, the control sequencer 103 connects the conductor 119.
and 124 to transmit the RPL1 and W signals to the LRU circuit 104 and data memory 107, respectively. In response to these signals, the contents of address bus 112 are transferred to conductor 4 in CAM 401.
It is written into the location of the least recently used word determined by bits above 32-435. At the same time, the word present on data bus 111 is written into data memory 107 at the address transmitted via cable 131. Priority circuit 444 is updated during period T3. Note that in the example described herein, no information associated with LRU circuit 106 or data memory 109 needed to be changed. Another example to consider is Example 1 where the desired word is not contained in data memory 107-109 and must be read from main memory 102.
This is a case corresponding to . In this example, none of the LRU circuits achieves matching during the T0 period, and T0
At the end of , control sequencer 103 accesses main memory 102 to obtain the desired word. Control sequencer 103 accesses main memory 102 by transmitting a main memory read signal over conductor 125.
When main memory 102 accesses the desired word, it is connected to main memory via conductor 126.
It responds by transmitting a memory ready signal and adding the desired memory word onto data bus 111. The control sequencer 103 responds to the main memory ready signal to read the cache data.
A ready signal is generated to inform processor 101 that data is present on data bus 111 and to perform the next step to update the LRU circuitry and data memory. After receiving the main memory ready signal, control sequencer 103 sends a T1 signal. The consequences of transmitting the T1 signal will first be described with reference to FIG. That is, the M2 signal is not transmitted via conductor 115 and data selector 203 is
Lead wires 232 to 23 to read CAM201
5, the address of the least recently used word transmitted from the priority circuit of FIG. The word read from CAM 201 is the address of the most recently used data word stored in data memory 108.
At the same time, a read is again performed on data memory 108 based on the address transmitted via cable 132, which is the address of the most recently used word. At the end of T1, the address of the most recently used word is added into latch 207 and stored in data memory 108.
The data being accessed from
It is added to a similar set of latches in memory 108. The same type of operation occurs in LRU circuits 104 and 1.
06 and data memories 107 and 109. During T2 period, LRU circuit 104 to cable 1
The address transmitted via 17 corresponds to the address of the most recently used word as defined by the address transmitted via conductors 232-235 from the priority circuit of FIG.
Written into the CAM 201 location.
Similarly, data that was being accessed from data memory 107 is written into data memory 108. With respect to the LRU circuit 104, the address on the address bus 112 indicates the address of the least recently used word in the priority circuit 44.
4 via conductors 432-435. Data present on data bus 111 is written into the most recently used word of data memory 107 at the address of the most recently used word. Similar operations are performed in LRU circuit 106 and data memory 109. During the T3 period,
The priority circuits of LRU circuits 104, 105 and 106 are updated to reflect the fact that the previous most recently used word is now the most recently used word. To explain the operation of the priority circuit shown in FIG.
See Example 3, which describes the behavior when the The operation of the priority circuit of FIG. 3 is similar to the operation of the priority circuits of priority circuit 444 and LRU circuit 106 of FIG. In the previous example, the most recently used word was word 1 in data memory 108;
It was the corresponding address in CAM location 1 of LRU circuit 105. During the alignment operation performed during T0, word 2 of CAM 201 is
It has been found that processor 101 contains the address it wishes to read. During T3, the priority circuit shown in FIG. 5 must be updated to reflect the fact that word 2 is now the most recently used word. However, word 1 still holds the most recently used word. Flip flops 322 to 327 are CAM201
and is used to maintain priorities regarding the order of use of words contained in data memory 108. NOR gates 328-331
decodes the information contained in flip-flops 322-327 to indicate which word is the most recently used word. for example,
NOR gate 328 is set to “1” via conductor 232
, this indicates that word 0 is the least recently used word.
OR gates 309-315 and AND gate 31
6-321 are used to determine which of flip-flops 322-327 should be changed during the priority circuit update period. Table 1 shows the meaning of these flip-flops set. For example, flip-flop 322
is set, flip-flop 322 transmits a "1" M0 signal to NOR gate 328 via conductor 301. flip
Flop 322 being set means that word 0 has been used more recently than word 1.

TABLE The functions performed by NOR gates 328-331 are shown in Table 2. Table 2 S0=01.02.03 S1=M01.12.13 S2=M02.M12.23 S3=M03.M13.M23 When “1” is transmitted via conductor 232,
Let us say that the S0 signal is being transmitted. When flip-flop 322 is set, the value of M01 in Table 2 is "1" and the value of 01 is 0.
It is. When flip-flop 322 is reset, the value of M01 is 0 and the value of 01 is 1. For example, flip-flop 322,
If 323 and 324 are reset, S
A zero signal will be transmitted via conductor 232. OR gates 309-315 and AND gate 3
Table 3 shows the operations at the time of updating 16 to 321.

[Table] The update takes place at time T3 when the RPL2 signal is transmitted from control sequencer 103 via conductor 120. T3 and RPL2 by AND gate 308, thereby OR gates 309-315 and AND gates 316-32.
1 is enabled. For example, when a "1" is transmitted on conductor 231 during an update period, flip-flops 324, 326 and 327 are reset. The "1" transmitted over conductor 231 indicates that word 3 is currently the most recently used word, so according to Table 1, flip-flops 324, 326 and 327 cannot be set. This is because these flip-flops indicate that word 0, word 1, and word 2 have each been accessed more recently than word 3. In order to more clearly explain the operation of the circuit shown in FIG. 3, the example shown before the alignment of word 2 takes place during the operation at time T0 will be described with reference to FIG. Row 501 is flip-flop 32
2 to 327 are shown. Once word 2 is determined to contain the desired word, the contents of word 2 are accessed and transmitted in both CAM 201 and data memory 108.
Stored in LRU circuit 104 and data memory 107. LRU circuit 104 and data
The most recently used word from memory 107 is sent to LRU circuit 105 and data memory 108.
and stored in word 2 of each of these memories. After this information is stored in word 2, word 2 becomes the most recently used word and flip-flops 322-327 must be updated accordingly. Since word 2 was the selected word, data selector 205 of FIG. 2 transmits a "1" on conductor 230. OR gates 309-315 and AND gates 316-321 respond to the "1" transmitted via conductor 230 to set flip-flop 327 and set flip-flops 323 and 325.
Reset. This is shown in row 502 of FIG. The word used most recently is Shogyo 5
Note that word 1 in 02. If the desired word in the next search operation is word 3, flip-flops 322-327 are updated during T3 to reflect the state shown in line 503. In the next search operation, if word 1 is found to contain the desired information, flip-flops 322-327 are updated to reflect the state shown in line 504. Note that the most recently used word here is word 0, which was not accessed during three search operations (during which periods words 2, 3, and 1 were accessed). It will be appreciated that the foregoing embodiments are illustrative of the principles of the invention and that other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.