JPS5698800A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5698800A
JPS5698800A JP147780A JP147780A JPS5698800A JP S5698800 A JPS5698800 A JP S5698800A JP 147780 A JP147780 A JP 147780A JP 147780 A JP147780 A JP 147780A JP S5698800 A JPS5698800 A JP S5698800A
Authority
JP
Japan
Prior art keywords
address
register
data
diagnostic
memory element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP147780A
Other languages
Japanese (ja)
Inventor
Kunio Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP147780A priority Critical patent/JPS5698800A/en
Publication of JPS5698800A publication Critical patent/JPS5698800A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To detect an error of an address system easily by fetching readout data from a memory element normally and by fetching and checking an address to which access is attained in a fault state.
CONSTITUTION: Diagnostic register 19 which can be set through soft-ware is provided and with its output, selecting circuit 21 for memory cards 11 is controlled to select data read out of memory element 12 or the output address of address buffer 14, thereby supplying it to data register 18. In a normal state, diagnostic register 19 is reset and selects the readout data of memory element 12. In a fault state, it enters into a diagnostic mode and set, and selecting circuit 21 transfers the address of address buffer 14 to readout register 18 for a check. Therefore, an error can be discriminated between a data system and address system, and while the diagnostic time is shortened, the fault estimation range can be reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP147780A 1980-01-09 1980-01-09 Memory device Pending JPS5698800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP147780A JPS5698800A (en) 1980-01-09 1980-01-09 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP147780A JPS5698800A (en) 1980-01-09 1980-01-09 Memory device

Publications (1)

Publication Number Publication Date
JPS5698800A true JPS5698800A (en) 1981-08-08

Family

ID=11502525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP147780A Pending JPS5698800A (en) 1980-01-09 1980-01-09 Memory device

Country Status (1)

Country Link
JP (1) JPS5698800A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7306140B2 (en) 2004-05-29 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit card system and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7306140B2 (en) 2004-05-29 2007-12-11 Samsung Electronics Co., Ltd. Integrated circuit card system and method thereof

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