JPS5593596A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5593596A
JPS5593596A JP23979A JP23979A JPS5593596A JP S5593596 A JPS5593596 A JP S5593596A JP 23979 A JP23979 A JP 23979A JP 23979 A JP23979 A JP 23979A JP S5593596 A JPS5593596 A JP S5593596A
Authority
JP
Japan
Prior art keywords
bit
anomaly
generated
register
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23979A
Other languages
Japanese (ja)
Inventor
Hiroyuki Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23979A priority Critical patent/JPS5593596A/en
Publication of JPS5593596A publication Critical patent/JPS5593596A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to detect all-bit anomaly to prevent the generation of the secondary fault even in the one-parity bit system by providing a memory where an anomaly detecting bit is written.
CONSTITUTION: When write information is received, a parity bit is generated in 1, and information is stored in elements 5 and 6 through registers 2 and 3. Meanwhile, write register 7 for an anomaly detection bit is always set to "0". Then, information "0" is always written onto element 8 from register 7. In case that a fault to set the output of memory elements to all bit "1" is generated, the output of anomaly bit detection memory 8 becomes "1", and an anomaly signal is generated through register 11 and OR circuit 14.
COPYRIGHT: (C)1980,JPO&Japio
JP23979A 1979-01-08 1979-01-08 Memory unit Pending JPS5593596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23979A JPS5593596A (en) 1979-01-08 1979-01-08 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23979A JPS5593596A (en) 1979-01-08 1979-01-08 Memory unit

Publications (1)

Publication Number Publication Date
JPS5593596A true JPS5593596A (en) 1980-07-16

Family

ID=11468410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23979A Pending JPS5593596A (en) 1979-01-08 1979-01-08 Memory unit

Country Status (1)

Country Link
JP (1) JPS5593596A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58167940U (en) * 1982-04-30 1983-11-09 株式会社島津製作所 Program data check device for complex arithmetic unit
JPS5958696A (en) * 1982-09-28 1984-04-04 Fujitsu Ltd Prom writer
JPS6461838A (en) * 1987-09-02 1989-03-08 Nec Corp Ic memory card

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58167940U (en) * 1982-04-30 1983-11-09 株式会社島津製作所 Program data check device for complex arithmetic unit
JPS5958696A (en) * 1982-09-28 1984-04-04 Fujitsu Ltd Prom writer
JPS6461838A (en) * 1987-09-02 1989-03-08 Nec Corp Ic memory card

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