JPS5542343A - Control system for memory unit - Google Patents

Control system for memory unit

Info

Publication number
JPS5542343A
JPS5542343A JP11499778A JP11499778A JPS5542343A JP S5542343 A JPS5542343 A JP S5542343A JP 11499778 A JP11499778 A JP 11499778A JP 11499778 A JP11499778 A JP 11499778A JP S5542343 A JPS5542343 A JP S5542343A
Authority
JP
Japan
Prior art keywords
signal
error
data
bit
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11499778A
Other languages
Japanese (ja)
Inventor
Moriyuki Takamura
Shohei Ikehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11499778A priority Critical patent/JPS5542343A/en
Publication of JPS5542343A publication Critical patent/JPS5542343A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to detect bit positions of a multibit error through software or only by adding a few circuits.
CONSTITUTION: Once error correction circuit ECC38 generates signal UNCOR15 indicating an uncorrectable error, operation signal GO16, operation mode signal OPC17 and write data DIN18 are supplied to a memory unit. Then, OPC17 assigns write operation and DIN18 generates known data such as all-"1" data. After the write operation, GO19 and OPC20 are generated again. Then, OPC20 assigns read operation and read data 14b is obtained. A bit-by-bit comparison between this read data 14b and known data 18 and a check are made and its result is generated as comparison error signal COMPE21. Therefore, error bit positions are discriminated by this signal and the detection becomes possible.
COPYRIGHT: (C)1980,JPO&Japio
JP11499778A 1978-09-19 1978-09-19 Control system for memory unit Pending JPS5542343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11499778A JPS5542343A (en) 1978-09-19 1978-09-19 Control system for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11499778A JPS5542343A (en) 1978-09-19 1978-09-19 Control system for memory unit

Publications (1)

Publication Number Publication Date
JPS5542343A true JPS5542343A (en) 1980-03-25

Family

ID=14651740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11499778A Pending JPS5542343A (en) 1978-09-19 1978-09-19 Control system for memory unit

Country Status (1)

Country Link
JP (1) JPS5542343A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173647A (en) * 1984-02-17 1985-09-07 Fujitsu Ltd Detecting system of error generating part of information processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173647A (en) * 1984-02-17 1985-09-07 Fujitsu Ltd Detecting system of error generating part of information processing unit
JPH0377546B2 (en) * 1984-02-17 1991-12-10 Fujitsu Ltd

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