JPS55108996A - Memory test system - Google Patents

Memory test system

Info

Publication number
JPS55108996A
JPS55108996A JP1411779A JP1411779A JPS55108996A JP S55108996 A JPS55108996 A JP S55108996A JP 1411779 A JP1411779 A JP 1411779A JP 1411779 A JP1411779 A JP 1411779A JP S55108996 A JPS55108996 A JP S55108996A
Authority
JP
Japan
Prior art keywords
memory
circuit part
control circuit
read
select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1411779A
Other languages
Japanese (ja)
Inventor
Giichi Oe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1411779A priority Critical patent/JPS55108996A/en
Publication of JPS55108996A publication Critical patent/JPS55108996A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To use hardware to shorten the test time by generating plural addresses for a tested memory to control read and write to the memory.
CONSTITUTION: This system is equipped with address generation parts 2 and 3 which generate plural address information of tested memory 6, address select circuit part 5 which selects plural generated address information, write signal control circuit part 13 for memory 6, read signal control circuit part 14 for memory 6, data control circuit part 15 which generates logical 1 or 0 to be entered onto memory 6, and signal select circuit parts which select either circuit 13 or 14. Then, the test of memory 6 is made possible, and read data of memory 6 is checked for correctness by circuits 16 to 17.
COPYRIGHT: (C)1980,JPO&Japio
JP1411779A 1979-02-09 1979-02-09 Memory test system Pending JPS55108996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1411779A JPS55108996A (en) 1979-02-09 1979-02-09 Memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1411779A JPS55108996A (en) 1979-02-09 1979-02-09 Memory test system

Publications (1)

Publication Number Publication Date
JPS55108996A true JPS55108996A (en) 1980-08-21

Family

ID=11852168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1411779A Pending JPS55108996A (en) 1979-02-09 1979-02-09 Memory test system

Country Status (1)

Country Link
JP (1) JPS55108996A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797641A (en) * 1980-12-10 1982-06-17 Ibm Integrated circuit chip capable of inspecting buried memory array
JPS6455800A (en) * 1987-08-14 1989-03-02 Ibm Memory testing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797641A (en) * 1980-12-10 1982-06-17 Ibm Integrated circuit chip capable of inspecting buried memory array
JPS6231439B2 (en) * 1980-12-10 1987-07-08 Intaanashonaru Bijinesu Mashiinzu Corp
JPS6455800A (en) * 1987-08-14 1989-03-02 Ibm Memory testing circuit

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