JPS56105400A - Simultaneous execution method for icrom write in and test - Google Patents

Simultaneous execution method for icrom write in and test

Info

Publication number
JPS56105400A
JPS56105400A JP782480A JP782480A JPS56105400A JP S56105400 A JPS56105400 A JP S56105400A JP 782480 A JP782480 A JP 782480A JP 782480 A JP782480 A JP 782480A JP S56105400 A JPS56105400 A JP S56105400A
Authority
JP
Japan
Prior art keywords
write
test
circuit
pattern generator
icrom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP782480A
Other languages
Japanese (ja)
Inventor
Takashi Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP782480A priority Critical patent/JPS56105400A/en
Publication of JPS56105400A publication Critical patent/JPS56105400A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

PURPOSE:To execute the write and the test simultaneously witg one set of devices, by using the address pattern generator and the write condition generating circuit of the IC memory test system to write data into the ROM and by using only the addres pattern generator to perform the test. CONSTITUTION:The address signal from address pattern generator 2 of IC memory test system 1 is applied to ICROM7, where the write state is selected through write condition generating circuit 6, to write information of RAM4. Next, when circuit 6 is turned off through switching circuit 5 of the system and the address signal from generator 2 is applied, corresponding written information of ROM7 is read out and is compared with storage information of RAM4 by deciding circuit 3 to test ROM7. Consequently, the write and the test of the ROM are executed simultaneously simply and rapidly by one set of the test system.
JP782480A 1980-01-28 1980-01-28 Simultaneous execution method for icrom write in and test Pending JPS56105400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP782480A JPS56105400A (en) 1980-01-28 1980-01-28 Simultaneous execution method for icrom write in and test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP782480A JPS56105400A (en) 1980-01-28 1980-01-28 Simultaneous execution method for icrom write in and test

Publications (1)

Publication Number Publication Date
JPS56105400A true JPS56105400A (en) 1981-08-21

Family

ID=11676338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP782480A Pending JPS56105400A (en) 1980-01-28 1980-01-28 Simultaneous execution method for icrom write in and test

Country Status (1)

Country Link
JP (1) JPS56105400A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544148A2 (en) * 1991-11-28 1993-06-02 Siemens Aktiengesellschaft Method for programming programmable integrated circuits
EP0591690A2 (en) * 1992-10-08 1994-04-13 Robert Bosch Gmbh Method and device for programming a non volatile memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544148A2 (en) * 1991-11-28 1993-06-02 Siemens Aktiengesellschaft Method for programming programmable integrated circuits
US5521833A (en) * 1991-11-28 1996-05-28 Siemens Aktiengesellschaft Method for programming programmable integrated circuits
EP0591690A2 (en) * 1992-10-08 1994-04-13 Robert Bosch Gmbh Method and device for programming a non volatile memory
EP0591690A3 (en) * 1992-10-08 1995-03-15 Bosch Gmbh Robert Method and device for programming a non volatile memory.

Similar Documents

Publication Publication Date Title
KR830009518A (en) Data Processing System for Parallel Processing
KR890008850A (en) Random Access Memory Unit
JPS6426243A (en) Hardware logical simulator
JPS6437125A (en) Cross coding method and device therefor
JPH02255925A (en) Method and device for memory test
KR850003009A (en) Apparatus and method for controlling a plurality of memory plates
JPS56105400A (en) Simultaneous execution method for icrom write in and test
JPS54142938A (en) Pattern generation system for display unit
JPS54134934A (en) Semiconductor memory device
JPS5712470A (en) Information processor having buffer memory
JPS5625295A (en) Semiconductor device
JPS56156978A (en) Memory control system
JPS57117056A (en) Microcomputer device
KR920003159A (en) Fast Testing of Programmable Logic Devices
JPS56169292A (en) Storage device
JPS6421557A (en) Method for testing memory
JPS55166745A (en) Maintenance information holding system by controller
JPS5794995A (en) Memory test system
JPS56127253A (en) Test pattern generator
JPS5573192A (en) Initial setting system for time-division channel
JPS54161238A (en) Testing method for magnetic bubble memory
JPS6441599A (en) Time switch circuit
JPS55122298A (en) Memory test method
JPS648589A (en) Semiconductor storage device
JPS55101200A (en) Memory unit