JPS648589A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS648589A
JPS648589A JP62164231A JP16423187A JPS648589A JP S648589 A JPS648589 A JP S648589A JP 62164231 A JP62164231 A JP 62164231A JP 16423187 A JP16423187 A JP 16423187A JP S648589 A JPS648589 A JP S648589A
Authority
JP
Japan
Prior art keywords
data
write
time
bit
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62164231A
Other languages
Japanese (ja)
Other versions
JP2641867B2 (en
Inventor
Akita Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62164231A priority Critical patent/JP2641867B2/en
Publication of JPS648589A publication Critical patent/JPS648589A/en
Application granted granted Critical
Publication of JP2641867B2 publication Critical patent/JP2641867B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To improve the output of defect detection by utilizing an address input terminal not required after the change of constitution to generate write data. CONSTITUTION:A pattern generator 9 generates 4 kinds of data patterns by using input data from an input buffer 8 and data from a terminal receiving a column address C9 being a disuse terminal at the time of revision of internal constitution. R/W switches 3-1-3-4 write a bit corresponding to the data pattern at the time of write to memory cell arrays 1-1-1-4 and a test circuit 6. Then the test circuit 6 checks the identity of the bit written at the time of write to each bit read from the memory cell arrays 1-1-1-4 at the time of readout and gives the result to an output buffer 7. Thus, the bit defect detection capability by the test pattern is improved.
JP62164231A 1987-06-30 1987-06-30 Semiconductor storage device Expired - Lifetime JP2641867B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164231A JP2641867B2 (en) 1987-06-30 1987-06-30 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164231A JP2641867B2 (en) 1987-06-30 1987-06-30 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS648589A true JPS648589A (en) 1989-01-12
JP2641867B2 JP2641867B2 (en) 1997-08-20

Family

ID=15789164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164231A Expired - Lifetime JP2641867B2 (en) 1987-06-30 1987-06-30 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JP2641867B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175094A (en) * 1983-03-22 1984-10-03 Mitsubishi Electric Corp Semiconductor memory
JPS60113167A (en) * 1983-11-25 1985-06-19 Hitachi Ltd Pattern generating method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175094A (en) * 1983-03-22 1984-10-03 Mitsubishi Electric Corp Semiconductor memory
JPS60113167A (en) * 1983-11-25 1985-06-19 Hitachi Ltd Pattern generating method

Also Published As

Publication number Publication date
JP2641867B2 (en) 1997-08-20

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