JPS5472924A - Semiconductor memory inspection equipment - Google Patents

Semiconductor memory inspection equipment

Info

Publication number
JPS5472924A
JPS5472924A JP13999477A JP13999477A JPS5472924A JP S5472924 A JPS5472924 A JP S5472924A JP 13999477 A JP13999477 A JP 13999477A JP 13999477 A JP13999477 A JP 13999477A JP S5472924 A JPS5472924 A JP S5472924A
Authority
JP
Japan
Prior art keywords
memory
memories
write data
commodity
inspected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13999477A
Other languages
Japanese (ja)
Inventor
Eiji Wada
Yoichi Asano
Akio Miwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13999477A priority Critical patent/JPS5472924A/en
Publication of JPS5472924A publication Critical patent/JPS5472924A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To improve the precision of inspection iterms by a simple constitution, by attaining parallel access to an inspected commodity and reference one with the same function for the formation of an expected value and by forming write data by a memory stored with special write data.
CONSTITUTION: In addition to inspected-commodity memory 3 and reference- commodity memory 3' with the same function as memory 3, test-pattern memory 2 stored with testing write data is provided. In order to supply address information AD and memory-operation control signal R/W from address generating circuit 1 to both memories 3 and 3' according to a fixed program, and to obtain write data from memory to memories 3 and 3', address information AD is supplied to memory 2 and output Di of memory 2 is to both memories 3 and 3'. Then, memories 3 and 3' are operated under the same conditions, and outputs of memories 3 and 3' are compared by comparing-coincidence circuit 4, so that decising signal (DO/NGO) will be outputted depending upon the result of the comparison.
COPYRIGHT: (C)1979,JPO&Japio
JP13999477A 1977-11-24 1977-11-24 Semiconductor memory inspection equipment Pending JPS5472924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13999477A JPS5472924A (en) 1977-11-24 1977-11-24 Semiconductor memory inspection equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13999477A JPS5472924A (en) 1977-11-24 1977-11-24 Semiconductor memory inspection equipment

Publications (1)

Publication Number Publication Date
JPS5472924A true JPS5472924A (en) 1979-06-11

Family

ID=15258452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13999477A Pending JPS5472924A (en) 1977-11-24 1977-11-24 Semiconductor memory inspection equipment

Country Status (1)

Country Link
JP (1) JPS5472924A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870174A (en) * 1981-09-29 1983-04-26 Fujitsu Ltd Test system for semiconductor ic memory
JPS61147356A (en) * 1984-12-20 1986-07-05 Toshiba Corp Testing device for memory module
KR100896585B1 (en) * 2000-09-28 2009-05-21 베리지 (싱가포르) 피티이. 엘티디. Memory tester has memory sets configurable for use as error catch ram, tag ram's, buffer memories and stimulus log ram

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870174A (en) * 1981-09-29 1983-04-26 Fujitsu Ltd Test system for semiconductor ic memory
JPS61147356A (en) * 1984-12-20 1986-07-05 Toshiba Corp Testing device for memory module
KR100896585B1 (en) * 2000-09-28 2009-05-21 베리지 (싱가포르) 피티이. 엘티디. Memory tester has memory sets configurable for use as error catch ram, tag ram's, buffer memories and stimulus log ram

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