JPS5690271A - Testing method for logic device - Google Patents

Testing method for logic device

Info

Publication number
JPS5690271A
JPS5690271A JP16864579A JP16864579A JPS5690271A JP S5690271 A JPS5690271 A JP S5690271A JP 16864579 A JP16864579 A JP 16864579A JP 16864579 A JP16864579 A JP 16864579A JP S5690271 A JPS5690271 A JP S5690271A
Authority
JP
Japan
Prior art keywords
scan
testing
group
memory element
scanned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16864579A
Other languages
Japanese (ja)
Other versions
JPS6210390B2 (en
Inventor
Masayuki Inagaki
Seiichiro Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16864579A priority Critical patent/JPS5690271A/en
Publication of JPS5690271A publication Critical patent/JPS5690271A/en
Publication of JPS6210390B2 publication Critical patent/JPS6210390B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To facilitate testing for the peripheral circuit of a memory element by a constitution wherein a scan-in scan-out flip-flop for testing only for one address and the number of line of an address designating signal is added to the memory element.
CONSTITUTION: By connecting a group 26 of a scan-in scan-out FF for testing with the memory element bit 21 of a designated address in parallel to each other, the testing on the periphery of the memory element is converted to two combination circuits 27 and 28 to be tested. As to the combination circuit 27 to be tested, a test pattern is scanned-in to a group of input FFs 24 through the intermediary of a scan-in scan-out path 29 for testing, while the result of the test is scanned-out from the group 26 of the scan-in scan-out FFs for testing. As to the combination circuit 28 to be tested, the test pattern is scanned-in to the group 26, while the result is scanned-out from the group of output FF. By such a constitution, a testing unit can be reduced and, accordingly, testing for the peripheral circuit of the memory element can be facilitated.
COPYRIGHT: (C)1981,JPO&Japio
JP16864579A 1979-12-25 1979-12-25 Testing method for logic device Granted JPS5690271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16864579A JPS5690271A (en) 1979-12-25 1979-12-25 Testing method for logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16864579A JPS5690271A (en) 1979-12-25 1979-12-25 Testing method for logic device

Publications (2)

Publication Number Publication Date
JPS5690271A true JPS5690271A (en) 1981-07-22
JPS6210390B2 JPS6210390B2 (en) 1987-03-05

Family

ID=15871867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16864579A Granted JPS5690271A (en) 1979-12-25 1979-12-25 Testing method for logic device

Country Status (1)

Country Link
JP (1) JPS5690271A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5859632A (en) * 1981-10-02 1983-04-08 Matsushita Electronics Corp Semiconductor integrated circuit
JPS643744A (en) * 1987-06-26 1989-01-09 Hitachi Ltd Lsi test method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5859632A (en) * 1981-10-02 1983-04-08 Matsushita Electronics Corp Semiconductor integrated circuit
JPS643744A (en) * 1987-06-26 1989-01-09 Hitachi Ltd Lsi test method

Also Published As

Publication number Publication date
JPS6210390B2 (en) 1987-03-05

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