JPS55163699A - Testing system for memory board - Google Patents
Testing system for memory boardInfo
- Publication number
- JPS55163699A JPS55163699A JP7165179A JP7165179A JPS55163699A JP S55163699 A JPS55163699 A JP S55163699A JP 7165179 A JP7165179 A JP 7165179A JP 7165179 A JP7165179 A JP 7165179A JP S55163699 A JPS55163699 A JP S55163699A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- test
- board
- bus
- memory board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE: To simplify the interface and then facilitate an easy real-time/dynamic test, by mounting the test circuit onto the memory board after formed into the LSI and then forming the pattern wiring between the packing position of the test circuit and the memory.
CONSTITUTION: The pin of test LSI6 is inserted into the socket attached to memory board 1'. The address bus, the output data bus, the input data bus and the control bus each are formed via the pattern wiring between the socket and memory 5 as well as between card edge connector 13 and memory 5. Connector 13 is opened when board 1' is tested. And with supply of the test mode indication from outside, LSI16 supplies the address or the data control to memory 5 to take the read data in. The test result is informed to the outside computer.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7165179A JPS55163699A (en) | 1979-06-06 | 1979-06-06 | Testing system for memory board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7165179A JPS55163699A (en) | 1979-06-06 | 1979-06-06 | Testing system for memory board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55163699A true JPS55163699A (en) | 1980-12-19 |
Family
ID=13466723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7165179A Pending JPS55163699A (en) | 1979-06-06 | 1979-06-06 | Testing system for memory board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55163699A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63241799A (en) * | 1987-03-16 | 1988-10-07 | シーメンス・アクチエンゲゼルシヤフト | Method and circuit apparatus for parallel writing of data into semiconductor memory |
KR20020014031A (en) * | 2000-08-14 | 2002-02-25 | 이국상 | Apparatus for testing semiconductor memory devices |
KR20020096840A (en) * | 2002-01-14 | 2002-12-31 | 주식회사 실리콘 테크 | Graphic Memory Tester using Graphic Board |
US7487413B2 (en) | 2005-04-07 | 2009-02-03 | Samsung Electronics Co., Ltd. | Memory module testing apparatus and method of testing memory modules |
-
1979
- 1979-06-06 JP JP7165179A patent/JPS55163699A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63241799A (en) * | 1987-03-16 | 1988-10-07 | シーメンス・アクチエンゲゼルシヤフト | Method and circuit apparatus for parallel writing of data into semiconductor memory |
KR20020014031A (en) * | 2000-08-14 | 2002-02-25 | 이국상 | Apparatus for testing semiconductor memory devices |
KR20020096840A (en) * | 2002-01-14 | 2002-12-31 | 주식회사 실리콘 테크 | Graphic Memory Tester using Graphic Board |
US7487413B2 (en) | 2005-04-07 | 2009-02-03 | Samsung Electronics Co., Ltd. | Memory module testing apparatus and method of testing memory modules |
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