KR20020014031A - Apparatus for testing semiconductor memory devices - Google Patents

Abstract

PURPOSE: A semiconductor memory device test apparatus is provided, which discriminates an error which is generated in an actual usage environment of the memory device. CONSTITUTION: The test apparatus(200) is embodied on a main board or a mother board of a personal computer, and can control a frequency and a timing of a DUT(Device Under Test) memory device during its operation, and can vary a voltage applied to the DUT memory device independently. A CPU(210) controls the whole operation of the test apparatus, and controls an operation control of each device and a signal transmission. A memory controller(220) controls the CPU, a DUT memory(280) and an SRAM(240). An IO controller(230) manages every kind of input/output functions and is connected to the memory controller through a PCI bus. An LCD(270) and a keyboard are user interfaces to control an operation of the apparatus, and an RS232(272) is an asynchronous serial port.

Description

Apparatus for testing semiconductor memory devices

The present invention relates to semiconductor integrated circuit test techniques. More specifically, the present invention relates to a memory test apparatus capable of inspecting characteristics of a memory device and selecting defective products in an environment in which a semiconductor memory device is actually used.

1 is a block diagram showing a schematic configuration of a test apparatus for a conventional general semiconductor memory device.

The items for testing memory devices can be broadly divided into DC test, AC test, and functional test. The DC test is to test the direct current characteristics of the memory device. Connect the unit to the terminal under test, apply a specified voltage (current), and measure the voltage (current) flowing through the terminal with the DC measurement unit. The open / short test, input current, output voltage, and supply current are measured. The AC test measures a timing of a semiconductor device, and applies a pulse signal to an input terminal to measure operating characteristics such as an input / output transport delay time, an output signal start time, and an end time. Functional test is to test the read / write function or mutual interference of each memory cell at the actual operation speed of the memory device. By applying a pulse that converts the test pattern produced by the pattern generator to the prescribed level, the device under unit (DUT) Compare the output signal of the DUT with the specified level. The result of this comparison is compared with the expected output pattern generated by the pattern generator to test the operation. This is typically done with a dynamic functional test that combines an AC test with a functional test.

The conventional test apparatus 100 illustrated in FIG. 1 includes a main station 110 and a test head 130, and tests the DUT 140. Peripherals such as disk 102 or keyboard 104 are used. The main station 110 is composed of a CPU 112, a power supply 114, a timing generator 118, a pattern generator 120, a waveform shaper 122, a fault bit memory 124, a comparator memory 126, and a bus. Send and receive data through 116. The test head 130 is usually mounted in a handler (not shown) and includes a driver 132, pin electronics 134 and 136, and a comparator 138.

The timing generator 118 is used to determine the test rate used for the AC test and the functional test, the delay of the clock required for waveform processing, the width of the timing, the output of the DUT element, and generate a strobe. The test rate and clock measurements can be controlled in real time.

The pattern generator 120 generates an input pattern and an output comparison pattern of the DUT 140, and its operation speed is determined by a rate signal output from the timing generator 118. In the case of the memory test, since the memory cells are physically arranged in order, a constant algorithm of test patterns (working, galloping, etc.) effective for detection of malfunction due to interference between multiple selection memory cells of the decoder is generated. Dedicated generator with arithmetic and judgment function of register called pattern generator (ALGP).

The waveform formatter 122 uses a test pattern generated by the pattern generator and a complex clock signal from the timing generator to generate return to zero (NRZ), non-return to zero (NRZ), and round by compensation (SBC). A logic waveform is generated and sent to the DUT 140 via the driver 132, pin electronics 134.

The driver 134 of the test head 130 amplifies the applied input voltage VIH / VIL and applies it to the DUT 140. Data from the DUT 140 is input to the comparator 138 via pin electronics 136 and compared to the expected pattern from the pattern generator 120 and stored in the fault bit memory 124.

These memory test apparatuses are increasingly developed as high-capacity, high-speed, and multi-pinning memory devices, and with the advent of EDO DRAM, SDRAM, RAM bus DRAM, and sync-link DRAM (SLDRAM), the test apparatus for testing them becomes faster. And it must be high precision, and it is necessary to suppress the cost increase by the increase of the test time according to the large capacity of a memory, and it is necessary to aim at miniaturization, low power consumption. To this end, a 250 MHz operation is realized by interleaving the pattern generator, the timing generator, the waveform shaper, and the logic comparator two by one to realize a 250 MHz operation. Was developed.

However, the main station 110 and the test head 130 of the conventional semiconductor test device are separated into separate devices, and the high speed signal transmission is performed by a cable connecting the main station 110 and the handler where the test head 130 is located. There are limitations and therefore limitations to high speed testing of large numbers of memory devices in parallel.

In addition, such high-speed test equipment is too expensive, and this price increase is getting worse as semiconductor memory devices improve.

On the other hand, the conventional test apparatus is impossible to test in the same environment as the environment in which the memory device is actually used. In particular, as the function of semiconductor memory devices improves, many types of defective electrical characteristics are generated according to the semiconductor production process, and memory device manufacturers manufacture electronic products such as computers using memory devices after shipment of the manufactured products. You will receive a lot of defect notifications from the company. However, depending on the type of failure, a test device used by a memory manufacturer may not detect such a defect.

In addition, set makers test memory devices using a test program developed by the company as part of the memory device arrival test method, which can not be implemented in a general memory semiconductor test device or takes a long time. For memory manufacturers, too much cost and time is required.

On the other hand, the memory device performs a reliability test after manufacturing, before supplying to the user, a burn-in test is a typical test. This burn-in test improves the reliability of the device supplied to the user by, for example, inspecting the memory device for a long time at a high temperature of 125 ° C. or more and selecting the short-lived device in advance. However, since the burn-in test apparatus must test a large number of devices in parallel, the burn-in test apparatus cannot keep up with the operating speed of the actual memory device.

Accordingly, an object of the present invention is to provide a test apparatus capable of properly identifying a defect that may occur in an actual use environment of a memory device.

Another object of the present invention is to provide a simple, inexpensive and compact test apparatus.

It is still another object of the present invention to provide a test apparatus that can be applied to a defect test and a burn-in test of a memory device.

Still another object of the present invention is to provide a test apparatus suitable for high speed and high capacity of a memory device.

1 is a block diagram showing an internal configuration of a general LSI test apparatus.

2 is a block diagram of a test apparatus according to the present invention;

3 is a program flow diagram in accordance with the present invention.

4 is a data timing diagram of a CPU and a memory bus in accordance with the present invention.

Description of the main symbols in the drawings

210: central process unit

220: memory controller

230: I / O (input / output) controller

240: static random access memory (SRAM)

250: VDD, CLK, SPD controller

260: read only memory (ROM)

270: liquid crystal display (LCD)

272: RS232

274: keyboard

280: device under test (DUT)

The test apparatus according to the present invention examines electrical characteristics of a memory semiconductor device used as a main memory based on a function of a chipset that connects functions of a CPU, a peripheral device, and a main memory to each other. Therefore, it is possible to program freely in a general PC environment, and to implement an electrical characteristic test of a memory semiconductor device by mounting an appropriate program on an actual transmit / receive signal generated from a CPU and a chipset, and test a plurality of parallel memory semiconductor devices.

The test apparatus according to the present invention allows the memory element to be verified in a PC environment, thereby ensuring high reliability that cannot be provided in the conventional memory test apparatus. In particular, by using a high-performance test pattern that cannot be provided in the conventional test apparatus, it is possible to significantly reduce the test error and accurately detect even the bit error, thereby enabling rapid post processing.

The test apparatus according to the present invention is a test apparatus for inspecting a semiconductor memory device, comprising: a central controller controlling overall operation of the test apparatus, a first memory element storing a program controlling an initial operation of the test apparatus; A second memory device in which the program is written, a memory device under test which functions as a main memory of the test apparatus, and controls operations of the second memory device and the memory device under test, A memory controller for adjusting timing, a user interface for inputting an input signal to the test apparatus by a user, a user interface representing a signal output from the test apparatus, an input / output controller for controlling the user interface and the first memory, and the input / output controller The clock of the memory device under test It is a voltage / clock controller that controls the voltage level.

Example

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described with reference to drawings.

2 is a configuration block diagram of a test apparatus according to the present invention. The test apparatus 200 includes a CPU 210, a memory controller 220, an input / output unit 230, an SRAM 240, a VDD / clock / speed controller 250, a ROM 260, and an LCD 270. And peripherals such as RS232 272, keyboard 274, and the DUT 280 is tested.

The test apparatus 200 according to the present invention is implemented on a main board or a mother board of a personal computer, and measures the frequency and timing of a memory element (ie, a DUT) during the operation of the apparatus 200. It can be freely adjusted according to the user's control. In addition, the test apparatus 200 may vary the voltage applied to the DUT memory device alone.

The CPU 210 controls the overall operation of the test apparatus according to the present invention, and controls the operation control and signal transmission of various elements inside the apparatus. The CPU 210 may be implemented with, for example, an Intel Pentium-based microprocessor or AMDK6-2, 450 MHz, and the memory controller 220, the I / O unit 230, and the SRAM (the system bus 290). And exchange data with the data.

The memory controller 220 controls the CPU 210, the DUT memory 280, and the SRAM 240. Operation frequency adjustment and timing adjustment of the DUT memory 280 are performed by the memory controller 220.

The I / O controller 230 integrally manages various input / output functions as well as a function of controlling various input / output devices. The I / O controller 230 is connected to the memory controller 220 by a bus 290, for example a PCI bus. The LCD 270 and keyboard 270 connected to the I / O controller 230 are user interfaces for inspecting the DUT memory 280 and controlling the operation of the device 200, and the RS232 272 is an asynchronous serial port. As an in-person PC interface, you can connect an external modem or mouse.

In the ROM 260, a basic input output system (BIOS) is stored. As shown in FIG. 3, the CPU 210 obtains data from the ROM 260 (step ①) and sends the data to the SRAM 240. (Step ②). CPU 210 executes this by taking a program from SRAM 240 (step ③).

The test apparatus 200 according to the present invention divides the cache memory (not shown) into two systems of code (instruction) and data to reduce cache access contention, thereby improving the efficiency of the cache memory. The code cache 212 is where signals coming through the bus interface unit (BIU) of the CPU 210 are temporarily stored before being decoded by the instruction decoding device. When an external signal received from the code cache 212 arrives, the instruction decoding device first accumulates it in the instruction fetch buffer, and continuously converts the external signal into a form that can be processed by the logical operation unit (ALU). do. The code cache 212 temporarily stores an external signal so that it can be obtained immediately without going through the BIU when the instruction decoding apparatus requires it. The code cache 212 stores a part of an operating system (OS). On the other hand, the data cache 214 is the operating system comes to the data cache 214, unlike that used in a typical PC motherboard.

The VDD, CLK, and SPD controllers 250 control the supply voltage, the clock, and the speed. The controller 250 includes a micro-computer (not shown) capable of applying a variable voltage to the DUT memory 280 and measuring the output voltage / current of the memory 280. The controller 250 is connected to the main board via, for example, a printer port.

In the test apparatus 200 according to the present invention, data execution of the CPU execution and the memory 280 bus is as shown in FIG. 4.

The test apparatus 200 according to the present invention has a system clock of up to 140 MHz, for example, and supports a test clock of 60 to 130 MHz, which can be arbitrarily selected by the user. In addition to open / short circuit checks, more than 30 data access check patterns can be used to check the DUT memory and variably apply VDD in the 2.7 to 7V voltage range. In addition, test conditions can be programmed, refresh current limit programs, current consumption detection of memory devices, automatic and manual test selection, memory type automatic recognition, and various types of memory devices such as SDRAM units and memory modules. , ECC, F / P, EDO, DDR and RAMBUS memory devices can be inspected.

The test apparatus according to the present invention supports all PC66 / 100/133 and is capable of testing the PC environment, is easy to operate and easy to handle, and also the production inspection of the RAM module, quality inspection (wearing inspection and import inspection), Failure analysis, module / unit verification and bit defect inspection (full function inspection of modules / units) are possible.

The test pattern according to the present invention provides short-term test, optimal test, detailed test and selective test function to suit various test needs. Short-term testing involves testing the DUT memory device in an optimal state or condition to find most common failures. Optimal testing can be used when testing under conditions that provide the best performance. Detailed testing is to test the DUT memory device in a worst-case condition or condition, which may find irregular random failure of the memory device. The selective test is a test that the user makes by creating a test program, and selects a test from a list of test types. The test results are presented to the user in various report formats.

The test apparatus according to the present invention does not use an automatic transfer device such as a handler, and a CPU and a chipset element are connected in a signal pattern on a substrate without using a cable for signal transmission.

In addition, the burn-in system in the form of a conventional chamber is provided with a blowing device to maintain a predetermined temperature throughout the chamber, and several burn-in boards are inserted in a storage form. In addition, since dozens to hundreds of memory semiconductor devices are connected in parallel to one burn-in board, the clock frequency of the drive board is not very high and the signal quality of the clock signal is poor. Therefore, the conventional burn-in system requires a lot of time because the inspection proceeds in a very low frequency range. However, when the burn-in check is performed using the present invention, since the same clock frequency as the actual application speed of the memory semiconductor device can be applied, not only the actual test burn-in can be performed but also the burn-in check of the memory semiconductor device. This eliminates the need for a separate circuit configuration (so-called long cycle), which simplifies the circuit, thus reducing the size of the memory semiconductor device and enabling more reliable test burn-in. .

According to the present invention, a memory device can be tested in an environment in which it is actually used, and a simple, inexpensive and compact test device can be implemented.

Claims (5)

A test apparatus for inspecting a semiconductor memory device, A central controller for controlling the overall operation of the test device; A first memory device in which a program for controlling an initial operation of the test apparatus is stored; A second memory element in which the program is written; A memory device under test functioning as a main memory function of the test device; A memory controller which controls operations of the second memory device and the memory device under test, and adjusts an operating frequency and a timing of the memory device under test; A user interface in which a user applies an input signal to the test device and indicates a signal output from the test device; An input / output controller for controlling the user interface and the first memory; And a voltage / clock controller connected to the input / output controller and controlling a clock and an applied voltage level of the memory device under test. The test apparatus of claim 1, further comprising a code cache in which a signal transmitted to the CPU is temporarily stored and a part of the operating system is stored, and a data cache in which the operating system is stored. The test apparatus according to claim 1 or 2, wherein the CPU takes data from the first memory device and writes the data to a second memory device, and the CPU takes a program from the second memory device and executes the program. . 3. The test apparatus of claim 1 or 2, wherein the voltage / clock controller comprises a module for measuring the output voltage and current of the memory. The test apparatus of claim 1, wherein the CPU, the first memory device, the second memory device, the memory controller, the input / output controller, and the voltage / clock controller are implemented on one circuit board.