KR100334660B1 - Timing clock controller of semiconductor memory test apparatus - Google Patents

Abstract

According to the present invention, when testing a semiconductor memory using a motherboard of a computer device, the clock applied to the memory can be adjusted so that product characteristics can be inspected for clock changes, thereby improving product quality. An object of the present invention is to provide a timing clock controller of a test apparatus.

This includes an oscillator for oscillating a predetermined clock frequency, a frequency variable part for adjusting the oscillator output of the oscillator according to a control signal applied from the outside and outputting the oscillator output to a semiconductor memory, and a frequency change signal input from a motherboard of a computer device. A clock adjustment module having a control unit which sends a control signal to the frequency variable unit so as to adjust the output of the oscillator and output the control signal; It is achieved by having an interface unit for applying a frequency change signal provided from the motherboard to the clock adjustment module.

Description

TIMING CLOCK CONTROLLER OF SEMICONDUCTOR MEMORY TEST APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing clock controller, and more particularly, to adjust a clock applied to a memory to be tested when testing a semiconductor memory using a motherboard of a PC or a computer device such as a workstation or a server. The present invention relates to a timing clock controller of a semiconductor memory test apparatus capable of inspecting a product characteristic against a clock change.

In general, in a device using a semiconductor memory such as synchronous dynamic random access memory (SDRAM), RAMBUS DRAM, or static random access memory (SRAM), in order to check the characteristics and reliability of the internal circuit after the device assembly process After mounting the assembled semiconductor memory device in the socket, the test is conducted using specialized equipment for expensive semiconductor memory test.

However, the price of a specialized semiconductor memory test device is high, which increases the cost of testing a single memory device, which not only lowers the price competitiveness of the enterprise, but also a device that is not an environment in which the memory device is actually installed and used. Since the PC motherboard, which is the environment in which the memory device is actually used, is not properly implemented, the test environment is inferior in accuracy and quality problems.

In order to solve such a problem, semiconductor device manufacturers have recently used a test method using a motherboard of a computer device such as a PC or a workstation or a server that actually uses the semiconductor device.

The method using the motherboard of such a computer device is to install a socket to detachably install a memory module or a semiconductor unit device on the motherboard, and then insert a memory module or a unit memory device to be tested in the socket, and then It is judged whether the semiconductor element is normal or bad by operating.

However, the timing of memory clocks (14.31818MHz) is fixed on the motherboards of computer devices (primarily Intel Pentium-CPU compatible series), so that the characteristics of timing clock changes cannot be examined.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to allow a clock to be checked for a clock change by adjusting a clock applied to a memory when testing a semiconductor memory using a motherboard of a computer device. To provide a timing clock controller of a semiconductor memory test apparatus to improve the quality of the.

1 is a block diagram of a timing clock controller of a semiconductor memory test apparatus according to the present invention;

2 and 3 are operational flowcharts of the present invention.

<Description of the symbols for the main parts of the drawings>

10: motherboard 20: clock adjustment module

21: oscillator 22: frequency variable part

23: control unit 40: interface unit

In accordance with another aspect of the present invention, there is provided a test apparatus for a semiconductor memory using a motherboard of a computer device, the apparatus including: a clock adjusting module for adjusting a clock frequency according to a frequency change signal provided from the motherboard and outputting the clock frequency to the semiconductor memory; ; Characterized in that the interface unit for applying a frequency change signal provided from the motherboard to the clock adjustment module.

The clock adjustment module includes an oscillator for oscillating a predetermined clock frequency; A frequency varying unit for adjusting the oscillation output of the oscillator according to a control signal applied from the outside and outputting the oscillator output to the semiconductor memory; And a control unit which sends a corresponding control signal to the frequency variable unit according to a frequency change signal input from the motherboard through the interface unit to adjust the output of the oscillator so as to output the control signal.

Hereinafter, with reference to the accompanying drawings the present invention will be described in detail.

1 is a block diagram of a timing clock controller of a semiconductor memory test apparatus according to an exemplary embodiment of the present invention, wherein a clock frequency is adjusted according to a frequency change signal provided from a CPU (not shown) of a motherboard 10. The clock adjustment module 20 outputs a clock adjustment module 20 to a semiconductor memory (not shown) mounted in a specific socket for the test of 10 and a frequency change signal provided from a CPU of the motherboard 10. It is composed of an interface unit 30 for applying.

The clock adjustment module 20 adjusts the oscillator 21 for oscillating a predetermined clock frequency (14.31818 MHz) and the oscillation output of the oscillator 21 in accordance with a control signal applied from the outside in the motherboard 10. The frequency variable part 22 outputs to the mounted semiconductor memory and the frequency variable part 22 sends a control signal to the frequency variable part 22 according to the frequency change signal input from the CPU through the interface unit 30. It consists of a control unit 23 to adjust the output of the oscillator 21 to output, the clock adjustment module 20 is supplied with power by a power supply (not shown).

The interface unit 30 is a three-wire bus interface using an I / O port of a conventional computer device.

The present invention configured as described above will be described with the flowchart of FIG.

First, when the operator inputs a key using a keyboard or the like not illustrated to check the product characteristic of the timing clock change, and outputs a frequency change signal from the motherboard 10, the controller 23 through the interface unit 30. It is input to (S10).

Accordingly, the control unit 23 compares the existing clock frequency setting value with the value of the currently input frequency change signal (S20). If the two values are the same, the control unit 23 outputs the existing clock frequency setting value as it is. Send the corresponding control signal. Accordingly, the frequency variable part 22 outputs the existing clock frequency setting value as it is, and in this case, the next command according to the predetermined program is performed (S30).

If the current clock frequency set value and the current input frequency change signal are not equal to each other, the controller 23 may output the frequency of the clock corresponding to the frequency change signal currently input to the frequency variable part 22. Send a control signal to the motherboard 10 so that the progress of the timing clock test stops through a signal line (not shown), etc., and also sends a reset signal to the motherboard 10 (S40). -S60).

Upon completion of the reset, under the control of the controller 23, the frequency variable part 22 outputs the adjusted clock frequency (14.31818 MHz ± 50%) to the semiconductor memory in the motherboard 10 so that the semiconductor memory is changed to the changed frequency. To be operated (S70).

Therefore, the semiconductor memory can be examined for timing clock changes.

On the other hand, unlike the above, as shown in Figure 3, when the clock change is required because the existing clock frequency set value and the current input frequency change signal value is not the same in step S20, according to the control of the controller 23 After the clock change is performed by the frequency variable unit 22 (S40), the process may proceed directly to step S30 without performing steps S50 to S70 of FIG.

The present invention is not limited to the above described embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

As described above, the present invention can improve the product quality since it is possible to examine the product characteristics of the timing clock when the semiconductor memory is tested in an actual mounting environment such as a motherboard of a computer device.

Claims (2)

In the test apparatus of the semiconductor memory using the motherboard of the computer device, A clock adjustment module for adjusting a clock frequency according to a frequency change signal provided from the motherboard and outputting the clock frequency to the semiconductor memory; An interface unit for applying a frequency change signal provided from the motherboard to the clock adjustment module; The clock adjusting module includes an oscillator for oscillating a predetermined clock frequency, a frequency variable part for adjusting the oscillator output of the oscillator according to a control signal applied from the outside, and outputting the oscillator output to the semiconductor memory, and from the motherboard through the interface unit. And a control unit which sends a control signal to the frequency variable unit according to an input frequency change signal to adjust the output of the oscillator and output the control signal. delete