TWI693410B - Chip test system and method - Google Patents

Chip test system and method Download PDF

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TWI693410B
TWI693410B TW108108252A TW108108252A TWI693410B TW I693410 B TWI693410 B TW I693410B TW 108108252 A TW108108252 A TW 108108252A TW 108108252 A TW108108252 A TW 108108252A TW I693410 B TWI693410 B TW I693410B
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wafer
machine
test
standard
chip
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TW108108252A
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TW202033968A (en
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朱國壔
謝雅瑄
洪孟群
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新唐科技股份有限公司
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Priority to CN201911422265.XA priority patent/CN111693846A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

A chip test system and method are provided. The test system includes a first PCB, a first chip carrier, a reference apparatus, a first chip test apparatus and a standard chip. The first chip carrier is electrically connected to the first PCB. The reference apparatus and the first chip test apparatus both have a function of writing parameters in a chip in order to test the chip such as trimming resistors of the chip. When the reference apparatus or the first chip test apparatus tests a chip, the chip is configured on the first chip carrier and the first PCB is electrically connected to the reference apparatus or the first chip test apparatus. Test the standard chip via the reference apparatus to get optimization parameters of the standard chip and then test the standard chip with the optimization parameters on the first chip test apparatus to get a first test result. If the first test result exceeds a predetermined standard, tune the first chip test apparatus until the predetermined standard is met. If the first test result meets the predetermined standard, calibration of the first chip test apparatus is accomplished.

Description

晶片測試系統及方法 Chip testing system and method

本發明係關於一種晶片測試系統及方法，尤其是關於一種用於大量生產晶片之晶片測試系統及方法，特別是關於降低各測試機台間之差異性。 The invention relates to a wafer testing system and method, in particular to a wafer testing system and method for mass production of wafers, and in particular to reducing the difference between test machines.

在晶片出貨前，必須透過測試機台對每一個晶片進行測試，例如對晶片上元件之電阻值做修整以得到最佳頻率，或是用以加強晶片穩定度等。一般來說，測試機台會先經過機台廠商的校正以符合當初所保證之規格，然而，即使每一個測試機台都符合規格，不同測試機台之間仍存在差異。除此之外，測試環境的差異亦造成了晶片測試的變異，例如，當測試晶片時，以晶片載台來設置晶片並以電路板來電連接測試機台及晶片載台，在習知的測試技術中，不同的測試機台電連接不同的晶片載台及電路板以同步進行大量的晶片測試，在這樣的情況下，測試環境的不同(晶片載台及電路板)造成了晶片測試的變異。 Before the chips are shipped, each chip must be tested through the test machine, for example, to modify the resistance of the components on the chip to obtain the best frequency, or to enhance the stability of the chip. Generally speaking, the test machine will be calibrated by the machine manufacturer to meet the specifications originally guaranteed. However, even if each test machine meets the specifications, there are still differences between different test machines. In addition, the differences in the test environment also cause variations in wafer testing. For example, when testing wafers, the wafer stage is used to set the wafer and the circuit board is used to electrically connect the test machine and the wafer stage. In the technology, different test machines are electrically connected to different wafer carriers and circuit boards to simultaneously perform a large number of wafer tests. In such cases, the different test environments (wafer carriers and circuit boards) cause variations in wafer testing.

並且，在習知的晶片測試方法中，會透過標準晶片(golden chip)對不同測試機台進行校正以縮小上述機台差異，其中，標準晶片之各種特性皆符合出貨標準，測試人員在測試待測晶片前會以不同測試機台對同一個標準晶片做測試，用以校正各個機台，然而，標準晶片在不同測試 機台上會隨著不同機台而被寫入不同的參數，這將導致機台校正過程無法最優化地降低機台間的差異。 In addition, in the conventional wafer test method, different test equipments are calibrated by using a standard chip (golden chip) to reduce the difference between the above equipments. Among them, the various characteristics of the standard chip meet the shipping standards, and testers are testing Before testing the wafer, the same standard wafer will be tested with different test machines to calibrate each machine. However, the standard wafer is tested in different Different parameters will be written on the machine with different machines, which will cause the machine calibration process to not optimally reduce the differences between the machines.

有鑑於上述習知技術的問題，本發明之一目的係提供一種晶片測試系統，其包含第一電路板、第一晶片載台、參考機台、第一晶片測試機台以及標準晶片(golden chip)。第一晶片載台係電連接第一電路板，參考機台以及第一晶片測試機台皆有對晶片寫入參數(例如修整電阻，trim resistor)以進行測試之功能，其中參考機台或第一晶片測試機台對晶片進行測試時，晶片係設置於第一晶片載台上，第一電路板係電連接參考機台或第一晶片測試機台。參考機台係測試標準晶片，以得到標準晶片之最佳化參數，並且基於最佳化參數，於第一晶片測試機台上對標準晶片進行測試以得到第一測試結果，若第一測試結果超出預設規格，則對第一晶片測試機台進行調機；若第一測試結果未超出預設規格，則代表第一晶片測試機台完成測試機台校正。 In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a chip testing system, which includes a first circuit board, a first chip carrier, a reference machine, a first chip testing machine, and a standard chip (golden chip) ). The first wafer stage is electrically connected to the first circuit board, and both the reference machine and the first wafer test machine have the function of writing parameters (such as trim resistors) to the wafer for testing. When a wafer testing machine tests a wafer, the wafer is set on the first wafer carrier, and the first circuit board is electrically connected to the reference machine or the first wafer testing machine. The reference machine tests the standard wafer to obtain the optimized parameters of the standard wafer, and based on the optimized parameters, the standard wafer is tested on the first wafer test machine to obtain the first test result, if the first test result If the preset specification is exceeded, the first wafer test machine is adjusted; if the first test result does not exceed the preset specification, it means that the first wafer test machine has completed the test machine calibration.

較佳地，最佳化參數可以透過參考機台寫入標準晶片之編碼區，並且編碼區對於第一晶片測試機台而言是唯讀的(read-only)。 Preferably, the optimized parameters can be written into the coding area of the standard wafer through the reference machine, and the coding area is read-only for the first wafer testing machine.

較佳地，最佳化參數可以透過參考機台儲存於遠端伺服器、可攜式存取裝置或電腦，並透過遠端伺服器、可攜式存取裝置或電腦輸入第一晶片測試機台，以在第一晶片測試機台上對標準晶片進行測試。 Preferably, the optimized parameters can be stored in the remote server, portable access device or computer through the reference machine, and input into the first chip testing machine through the remote server, portable access device or computer To test standard wafers on the first wafer testing machine.

較佳地，最佳化參數可以透過電腦輸入第一晶片測試機台，以在第一晶片測試機台上對標準晶片進行測試。 Preferably, the optimized parameters can be input into the first wafer testing machine through a computer to test the standard wafer on the first wafer testing machine.

較佳地，最佳化參數可以關於標準晶片上之元件之電阻值或用以加強標準晶片之穩定度之編碼。 Preferably, the optimization parameter may be related to the resistance value of the element on the standard chip or the code used to enhance the stability of the standard chip.

根據本發明之另一目的提供一種晶片測試方法，其包含測試機台校正階段以及晶片測試階段。測試機台校正階段係對具有對晶片寫入參數以進行測試之功能之第一晶片測試機台進行校正，使第一晶片測試機台相對於同樣具有對晶片寫入參數以進行測試之功能之參考機台而言符合預設規格，測試機台校正階段包含：將標準晶片(golden chip)設置於第一晶片載台，第一晶片載台係電連接第一電路板，並且第一電路板電連接參考機台；對標準晶片進行測試，以得到標準晶片之最佳化參數；將第一晶片載台、設置於第一晶片載台之標準晶片以及電連接第一晶片載台之第一電路板改以電連接於第一晶片測試機台；以及基於最佳化參數，於第一晶片測試機台上對標準晶片進行測試以得到第一測試結果，若第一測試結果超出預設規格，則對第一晶片測試機台進行調機；若第一測試結果未超出預設規格，則代表第一晶片測試機台完成測試機台校正階段。晶片測試階段係對待測晶片進行測試，其包含：將待測晶片設置於第一晶片載台，第一晶片載台電連接第一電路板，並將第一電路板電連接完成測試機台校正階段之第一晶片測試機台；以及於第一晶片測試機台上對待測晶片進行測試。 According to another object of the present invention, a wafer testing method is provided, which includes a calibration stage of a test machine and a wafer testing stage. The testing machine calibration stage is to calibrate the first wafer testing machine with the function of writing parameters to the wafer for testing, so that the first wafer testing machine has the function of writing parameters to the wafer for testing as well The reference machine meets the preset specifications. The calibration stage of the test machine includes: setting a standard chip (golden chip) on the first wafer stage, the first wafer stage is electrically connected to the first circuit board, and the first circuit board Electrically connect to the reference machine; test the standard wafer to obtain the optimized parameters of the standard wafer; connect the first wafer stage, the standard wafer placed on the first wafer stage and the first electrically connected to the first wafer stage The circuit board is changed to be electrically connected to the first wafer testing machine; and based on the optimized parameters, the standard wafer is tested on the first wafer testing machine to obtain the first test result, if the first test result exceeds the preset specification , The first wafer test machine is adjusted; if the first test result does not exceed the preset specification, it means that the first wafer test machine completes the test machine calibration stage. The wafer test stage is to test the wafer to be tested, which includes: setting the wafer to be tested on the first wafer stage, the first wafer stage is electrically connected to the first circuit board, and the first circuit board is electrically connected to complete the test machine calibration stage The first wafer testing machine; and testing the wafer to be tested on the first wafer testing machine.

較佳地，最佳化參數可以透過參考機台寫入標準晶片之編碼區，並且編碼區對於第一晶片測試機台而言是唯讀的。 Preferably, the optimized parameters can be written into the coding area of the standard wafer through the reference machine, and the coding area is read-only for the first wafer testing machine.

較佳地，最佳化參數可以透過參考機台儲存於遠端伺服器、可攜式存取裝置或電腦，並透過遠端伺服器、可攜式存取裝置或電腦輸入第一晶片測試機台，以在第一晶片測試機台上對標準晶片進行測試。 Preferably, the optimized parameters can be stored in the remote server, portable access device or computer through the reference machine, and input into the first chip testing machine through the remote server, portable access device or computer To test standard wafers on the first wafer testing machine.

較佳地，最佳化參數可以透過電腦輸入第一晶片測試機台，以在第一晶片測試機台上對標準晶片進行測試。 Preferably, the optimized parameters can be input into the first wafer testing machine through a computer to test the standard wafer on the first wafer testing machine.

較佳地，最佳化參數可以關於標準晶片上之元件之電阻值或用以加強標準晶片之穩定度之編碼。 Preferably, the optimization parameter may be related to the resistance value of the element on the standard chip or the code used to enhance the stability of the standard chip.

如上所述之晶片測試系統及方法，其相較於習知技藝之差異主要在於：在不同的晶片測試機台測試標準晶片時係基於同一組最佳化參數，且使用同樣的晶片載台及電路板以減少測試變異，所到得的測試結果能夠更真實地呈現機台之間的差異，以在測試機台校正階段提供校正人員更完整的資訊，不只校正各機台符合規格，更能降低各機台之間的差異，進一步提升了被測試的不同晶片之間的一致性。 The difference between the above-mentioned wafer test system and method compared to the conventional technique is mainly that: when testing standard wafers on different wafer test machines, the same set of optimized parameters are used, and the same wafer stage and Circuit board to reduce test variation, the obtained test results can more realistically show the differences between the machines, so as to provide more complete information for the calibration personnel during the test machine calibration stage, not only to correct each machine to meet the specifications, but also to Reduce the differences between the various machines, and further improve the consistency between the different wafers being tested.

100:標準晶片 100: standard chip

101:參考機台 101: Reference machine

102:第一晶片測試機台 102: First wafer testing machine

1021:第一電路板 1021: First circuit board

1022:第一晶片載台 1022: First wafer stage

S210~S214、S220~S222:步驟 S210~S214, S220~S222: Steps

第1圖係繪示根據本發明之一實施例之晶片測試系統之方塊圖。 FIG. 1 is a block diagram of a wafer testing system according to an embodiment of the invention.

第2圖係繪示根據本發明之一實施例之晶片測試方法之流程圖。 FIG. 2 is a flowchart of a wafer testing method according to an embodiment of the invention.

為利貴審查委員瞭解本發明之技術特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的申請專利範圍，合先敘明。 In order to facilitate your examination committee to understand the technical features, content and advantages of the present invention and the achievable effects, the present invention is described in detail in conjunction with the drawings and in the form of expressions of the embodiments, and the drawings used therein, which The main purpose is only for illustration and auxiliary description, not necessarily the true proportion and precise configuration after the implementation of the present invention, so the ratio and configuration relationship of the attached drawings should not be interpreted and limited to the patent application scope of the present invention in actual implementation , He Xianming.

請參照第1圖，其繪示根據本發明之一實施例之晶片測試系統方塊圖。如第1圖所示，晶片測試系統包含：標準晶片100、參考機台101、第一晶片測試機台102、第一電路板1021以及第一晶片載台1022。標準晶片(golden chip)100係一符合出貨規格之晶片，參考機台101以及第一晶片測試機台102係功能上大致相同之機台，其可對相同之至少一種晶片寫入參數以進行測試，其中所述之寫入參數係指對晶片上元件之可調特性進行調整，例如修整電阻(trim resistor)等最佳化設定，以加強晶片之穩定度；第一晶片載台1022用以裝載晶片；第一電路板1021則在晶片測試中用以電連接晶片及晶片測試機台。 Please refer to FIG. 1, which illustrates a block diagram of a wafer testing system according to an embodiment of the present invention. As shown in FIG. 1, the wafer test system includes: a standard wafer 100, a reference machine 101, a first wafer test machine 102, a first circuit board 1021, and a first wafer carrier 1022. The standard chip (golden chip) 100 is a chip that conforms to the shipping specifications. The reference machine 101 and the first chip testing machine 102 are machines with substantially the same function, which can write parameters to at least one kind of chip Test, where the write parameters refer to the adjustment of the adjustable characteristics of the elements on the chip, such as trim resistors and other optimized settings to enhance the stability of the chip; the first chip stage 1022 is used to Loading the wafer; the first circuit board 1021 is used to electrically connect the wafer and the wafer testing machine during wafer testing.

請參照第2圖，其繪示根據本發明之一實施例之晶片測試方法之流程圖。本發明之晶片測試方法主要包含兩步驟(S210~S220)，即步驟S210之測試機台校正階段，以及步驟S220之晶片測試階段，詳細說明如下： Please refer to FIG. 2, which illustrates a flowchart of a wafer testing method according to an embodiment of the invention. The wafer testing method of the present invention mainly includes two steps (S210-S220), namely, the test machine calibration stage of step S210, and the wafer testing stage of step S220. The detailed description is as follows:

步驟S210：在測試機台校正階段對第一晶片測試機台102進行校正，使第一晶片測試機台102與參考機台101不僅符合機台規格，兩機台間的差異更得以縮小。如前所述，每個測試機台都會先經過機台廠商的校正以符合當初保證之規格，然而，即使每一個測試機台都符合其規格，不同測試機台之間仍存在差異，故最小化機台之間的差異是必要的，根據本實施例，步驟S210可進一步以下述之步驟(S211~S214)來說明： Step S210: the first wafer testing machine 102 is calibrated in the testing machine calibration stage, so that the first wafer testing machine 102 and the reference machine 101 not only conform to the machine specifications, but also the difference between the two machines is reduced. As mentioned earlier, each test machine will be calibrated by the machine manufacturer to meet the original guaranteed specifications. However, even if each test machine meets its specifications, there are still differences between different test machines, so the minimum The difference between the chemical machines is necessary. According to this embodiment, step S210 can be further explained by the following steps (S211-S214):

步驟S211：將標準晶片100設置於第一晶片載台1022，第一晶片載台1022電連接第一電路板1021，且第一電路板1021電連接參考機台101。其連接關係如第1圖所繪示(第1圖實線)。 Step S211: The standard wafer 100 is placed on the first wafer stage 1022, the first wafer stage 1022 is electrically connected to the first circuit board 1021, and the first circuit board 1021 is electrically connected to the reference machine 101. The connection relationship is as shown in Figure 1 (solid line in Figure 1).

步驟S212：對標準晶片100進行測試，得到標準晶片100之最佳化參數，並透過參考機台101將最佳化參數寫入標準晶片100之編碼區。在此步驟 中，參考機台101對標準晶片100進行測試，並根據測試結果調整標準晶片100上元件之可調整特性，並將對應於標準晶片100之最佳化測試結果(以下稱為標準測試結果)之各種特性設定值設定為標準晶片100之最佳化參數。 Step S212: Test the standard wafer 100 to obtain the optimized parameters of the standard wafer 100, and write the optimized parameters into the coding area of the standard wafer 100 through the reference machine 101. In this step In reference, the reference machine 101 tests the standard wafer 100 and adjusts the adjustable characteristics of the components on the standard wafer 100 according to the test results, and the optimized test results corresponding to the standard wafer 100 (hereinafter referred to as standard test results) Various characteristic setting values are set as the optimized parameters of the standard wafer 100.

步驟S213：將標準晶片100、第一晶片載台1022以及第一電路板1021改以電連接於第一晶片測試機台102。其連接關係如第1圖所繪示(第1圖虛線)。 Step S213: The standard wafer 100, the first wafer stage 1022 and the first circuit board 1021 are changed to be electrically connected to the first wafer testing machine 102. The connection relationship is as shown in Figure 1 (dotted line in Figure 1).

步驟S214：基於最佳化參數，於第一晶片測試機台102上對標準晶片100進行測試以得到第一測試結果。在此步驟中，標準晶片100之最佳化參數係步驟S212中所得之最佳化參數且維持不變，其中，最佳化參數可以是在執行步驟S212之後透過參考機台101寫入標準晶片100之編碼區(未繪示)，此編碼區對於第一晶片測試機台102而言是唯讀的(read-only)；或者根據本發明一實施例，最佳化參數可以是在執行步驟S212之後透過參考機台101儲存於遠端伺服器、可攜式存取裝置或電腦，上述裝置中的任一種再將最佳化參數輸入第一晶片測試機台102；或者根據本發明另一實施例，最佳化參數可以是在執行步驟S214之前透過測試人員輸入第一晶片測試機台102。基於最佳化參數，第一晶片測試機台102直接對標準晶片100進行測試，並得到第一測試結果，此第一測試結果與上述標準測試結果進行比較，若第一測試結果與標準測試結果之間的差異符合預設規格，則代表第一晶片測試機台102完成測試機台校正階段，即最優化地降低第一晶片測試機台102與參考機台101之間的機台差異，在下述對待測晶片進行測試的階段中，由於第一晶片測試機台102與參考機台101之間的差異已降低，第一晶片測試機台102與參考機台101得以同時進行晶片測試以提升產量。若第一測試結果與標準測試結果之間的差異不符合預設規格，則代表必須 進一步對第一晶片測試機台102進行調機，直到第一晶片測試機台102完成此測試機台校正階段。 Step S214: Based on the optimized parameters, the standard wafer 100 is tested on the first wafer testing machine 102 to obtain a first test result. In this step, the optimized parameters of the standard wafer 100 are the optimized parameters obtained in step S212 and remain unchanged, wherein the optimized parameters may be written into the standard wafer through the reference machine 101 after performing step S212 100 coding region (not shown), this coding region is read-only for the first wafer testing machine 102; or according to an embodiment of the present invention, the optimization parameter may be in the execution step After S212, it is stored in a remote server, a portable access device or a computer through the reference machine 101, and any one of the above-mentioned devices then inputs the optimized parameters into the first chip testing machine 102; or another according to the present invention In an embodiment, the optimization parameter may be input by the tester to the first wafer testing machine 102 before performing step S214. Based on the optimized parameters, the first wafer testing machine 102 directly tests the standard wafer 100 and obtains the first test result. This first test result is compared with the above-mentioned standard test result. If the first test result and the standard test result If the difference between them meets the preset specifications, it means that the first wafer test machine 102 has completed the test machine calibration phase, that is, the difference between the first wafer test machine 102 and the reference machine 101 is optimally reduced. In the stage of testing the wafer to be tested, since the difference between the first wafer testing machine 102 and the reference machine 101 has been reduced, the first wafer testing machine 102 and the reference machine 101 can simultaneously perform wafer testing to increase the yield . If the difference between the first test result and the standard test result does not meet the preset specifications, the representative must The first wafer test machine 102 is further adjusted until the first wafer test machine 102 completes the test machine calibration stage.

本發明相較於習知技術之差異主要在於：在不同的晶片測試機台(參考機台以及第一晶片測試機台)測試標準晶片時，係基於同樣的最佳化參數及同一組晶片載台及電路板，而不是如習知技術於第一晶片測試機台上以標準晶片的另一組最佳化參數來測試標準晶片，本發明所揭露的技術特徵係固定最佳化參數，再根據標準晶片於不同的晶片測試機台得到的不同測試結果來調整機台，直到不同的晶片測試機台能得到符合預設規格的測試結果。 The difference between the present invention and the conventional technology mainly lies in that: when testing standard wafers on different wafer testing machines (reference machine and first wafer testing machine), it is based on the same optimized parameters and the same set of wafer load Instead of testing the standard wafer with another set of optimized parameters of the standard wafer on the first wafer testing machine as in the conventional technology, the technical feature disclosed in the present invention is to fix the optimized parameters, and then The machine is adjusted according to the different test results obtained by the standard wafer on different wafer test machines until different wafer test machines can obtain test results that meet the preset specifications.

當第一晶片測試機台102在測試機台校正階段完成校正，即可進入晶片測試階段對待測晶片進行測試(步驟S220)，步驟S220可進一步以下述之步驟(S221~S222)來說明： When the first wafer testing machine 102 completes the calibration in the testing machine calibration stage, it can enter the wafer testing stage to test the wafer to be tested (step S220). Step S220 can be further described by the following steps (S221~S222):

步驟S221：將待測晶片設置於第一晶片載台1022，第一晶片載台1022電連接第一電路板1021，並將第一電路板1021電連接完成測試機台校正階段之第一晶片測試機台102。 Step S221: the wafer to be tested is set on the first wafer stage 1022, the first wafer stage 1022 is electrically connected to the first circuit board 1021, and the first circuit board 1021 is electrically connected to complete the first wafer test in the calibration stage of the testing machine Machine 102.

步驟S222：於第一晶片測試機台102上對待測晶片進行測試。 Step S222: Test the wafer to be tested on the first wafer testing machine 102.

當需要大量測試晶片時，可在更多的測試機台上重複上述的晶片測試方法，降低多個晶片測試機台間的差異。 When a large number of wafers need to be tested, the above wafer testing method can be repeated on more test machines to reduce the differences between multiple wafer test machines.

根據本發明所揭露之晶片測試系統及方法係基於標準晶片之同一組最佳化參數來進行不同的晶片測試機台的校正，並以同一組電路板及晶片載台進行校正以減少量測變異，其相較於習知技術能夠更優化地降低機台之間的差異，進一步提升了出貨晶片之間的一致性。 The wafer testing system and method disclosed according to the present invention are based on the same set of optimized parameters of standard wafers to calibrate different wafer testing machines, and are calibrated with the same set of circuit boards and wafer carriers to reduce measurement variation Compared with the conventional technology, it can more optimally reduce the difference between the machines, and further improve the consistency of the shipped chips.

以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above is only exemplary, and not restrictive. Any equivalent modifications or changes made without departing from the spirit and scope of the present invention shall be included in the scope of the attached patent application.

100:標準晶片 100: standard chip

101:參考機台 101: Reference machine

102:第一晶片測試機台 102: First wafer testing machine

1021:第一電路板 1021: First circuit board

1022:第一晶片載台 1022: First wafer stage

Claims (8)

一種晶片測試系統，其包含：一第一電路板；一第一晶片載台，係電連接該第一電路板；一參考機台以及一第一晶片測試機台，皆有對一晶片寫入參數以進行測試之功能，其中該參考機台或該第一晶片測試機台對該晶片進行測試時，該晶片係設置於該第一晶片載台上，該第一電路板係電連接該參考機台或該第一晶片測試機台；以及一標準晶片，該參考機台係測試該標準晶片，以得到該標準晶片之一最佳化參數，並且基於該最佳化參數，於該第一晶片測試機台上對該標準晶片進行測試以得到一第一測試結果，若該第一測試結果超出一預設規格，則對該第一晶片測試機台進行調機；若該第一測試結果未超出該預設規格，則代表該第一晶片測試機台完成一測試機台校正；其中該最佳化參數係關於該標準晶片上之一元件之電阻值或用以加強該標準晶片之穩定度之編碼。 A chip test system includes: a first circuit board; a first chip carrier, which is electrically connected to the first circuit board; a reference machine and a first chip test machine, both of which write to a chip The parameter is used for testing. When the reference machine or the first wafer testing machine tests the wafer, the wafer is set on the first wafer stage, and the first circuit board is electrically connected to the reference Machine or the first wafer testing machine; and a standard wafer, the reference machine tests the standard wafer to obtain one of the optimized parameters of the standard wafer, and based on the optimized parameter, the first Test the standard wafer on the wafer testing machine to obtain a first test result, if the first test result exceeds a preset specification, adjust the first wafer testing machine; if the first test result If the preset specification is not exceeded, it means that the first chip test machine has completed a test machine calibration; wherein the optimized parameter is related to the resistance value of a component on the standard chip or used to enhance the stability of the standard chip Degree of coding. 如請求項1所述之晶片測試系統，其中該最佳化參數係透過該參考機台寫入該標準晶片之一編碼區，並且該編碼區對於該第一晶片測試機台而言是唯讀的。 The wafer test system according to claim 1, wherein the optimization parameter is written into one of the coding regions of the standard wafer through the reference machine, and the coding region is read-only for the first wafer testing machine of. 如請求項1所述之晶片測試系統，其中該最佳化參數係透過該參考機台儲存於一遠端伺服器、一可攜式存取裝置或一電腦，並透過該遠端伺服器、該可攜式存取裝置或該電腦輸入該第一晶片測試機台，以在該第一晶片測試機台上對該標準晶片進行 測試。 The chip test system according to claim 1, wherein the optimized parameters are stored in a remote server, a portable access device or a computer through the reference machine, and through the remote server, The portable access device or the computer inputs the first wafer testing machine to perform the standard wafer on the first wafer testing machine test. 如請求項1所述之晶片測試系統，其中該最佳化參數係透過一電腦輸入該第一晶片測試機台，以在該第一晶片測試機台上對該標準晶片進行測試。 The wafer testing system according to claim 1, wherein the optimization parameter is input to the first wafer testing machine through a computer to test the standard wafer on the first wafer testing machine. 一種晶片測試方法，其包含：一測試機台校正階段，該測試機台校正階段係對具有對一晶片寫入參數以進行測試之功能之一第一晶片測試機台進行校正，使該第一晶片測試機台相對於同樣具有對一晶片寫入參數以進行測試之功能之一參考機台而言符合一預設規格，該測試機台校正階段包含：將一標準晶片設置於一第一晶片載台，該第一晶片載台係電連接一第一電路板，並且該第一電路板電連接該參考機台；對該標準晶片進行測試，以得到該標準晶片之一最佳化參數；將該第一晶片載台、設置於該第一晶片載台之該標準晶片以及電連接該第一晶片載台之該第一電路板改以電連接於該第一晶片測試機台；以及基於該最佳化參數，於該第一晶片測試機台上對該標準晶片進行測試以得到一第一測試結果，若該第一測試結果超出一預設規格，則對該第一晶片測試機台進行調機；若該第一測試結果未超出該預設規格，則代表該第一晶片測試機台完成該測試機台校正階段；以及一晶片測試階段，係對一待測晶片進行測試，其包含： 將該待測晶片設置於該第一晶片載台，該第一晶片載台電連接該第一電路板，並將該第一電路板電連接完成該測試機台校正階段之該第一晶片測試機台；以及於該第一晶片測試機台上對該待測晶片進行測試；其中該最佳化參數係關於該標準晶片上之一元件之電阻值或用以加強該標準晶片之穩定度之編碼。 A wafer testing method includes: a testing machine calibration stage that calibrates a first wafer testing machine that has the function of writing parameters to a wafer for testing so that the first The wafer testing machine meets a preset specification relative to a reference machine that also has the function of writing parameters to a wafer for testing. The calibration stage of the testing machine includes: setting a standard wafer on a first wafer A stage, the first wafer stage is electrically connected to a first circuit board, and the first circuit board is electrically connected to the reference machine; testing the standard wafer to obtain one of the optimized parameters of the standard wafer; Changing the first wafer stage, the standard wafer provided on the first wafer stage, and the first circuit board electrically connected to the first wafer stage to be electrically connected to the first wafer testing machine; and based on The optimized parameter, testing the standard wafer on the first wafer testing machine to obtain a first test result, and if the first test result exceeds a preset specification, then testing the first wafer testing machine Adjust the machine; if the first test result does not exceed the preset specification, it means that the first chip test machine completes the test machine calibration stage; and a chip test stage is to test a chip to be tested, which contain: The wafer to be tested is set on the first wafer stage, the first wafer stage is electrically connected to the first circuit board, and the first circuit board is electrically connected to the first wafer testing machine that completes the calibration stage of the testing machine Test; and test the wafer under test on the first wafer testing machine; wherein the optimization parameter is about the resistance value of an element on the standard wafer or the code used to enhance the stability of the standard wafer . 如請求項5所述之晶片測試方法，其中該最佳化參數係透過該參考機台寫入該標準晶片之一編碼區，並且該編碼區對於該第一晶片測試機台而言是唯讀的。 The wafer testing method as described in claim 5, wherein the optimization parameter is written into one of the coding regions of the standard wafer through the reference machine, and the coding region is read-only for the first wafer testing machine of. 如請求項5所述之晶片測試方法，其中該最佳化參數係透過該參考機台儲存於一遠端伺服器、一可攜式存取裝置或一電腦，並透過該遠端伺服器、該可攜式存取裝置或該電腦輸入該第一晶片測試機台，以在該第一晶片測試機台上對該標準晶片進行測試。 The chip testing method as described in claim 5, wherein the optimized parameters are stored in a remote server, a portable access device, or a computer through the reference machine, and through the remote server, The portable access device or the computer inputs the first wafer testing machine to test the standard wafer on the first wafer testing machine. 如請求項5所述之晶片測試方法，其中該最佳化參數係透過一電腦輸入該第一晶片測試機台，以在該第一晶片測試機台上對該標準晶片進行測試。 The wafer testing method according to claim 5, wherein the optimized parameter is input to the first wafer testing machine through a computer to test the standard wafer on the first wafer testing machine.
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