TWI606246B - System for testing non-boundary scan chip and peripheral circuit thereof base on boundary scan and method thereof - Google Patents

Description

System and method for testing non-boundary scan wafer and its peripheral lines based on boundary scan

[0001] A test system and method thereof, and more particularly to a system and method for testing a non-boundary scan wafer and its peripheral lines based on boundary scan.

[0002] Existing testing of boundary scan wafers with each other is performed by boundary scan technology, whereas when there are non-boundary scan wafers in the wiring between boundary scan wafers, boundary scan wafers and non-boundary scan wafers are mutually The connection cannot be made through boundary scan technology. In summary, it has been known in the prior art that the prior art has not been able to test non-boundary scanning wafers by boundary scanning, and therefore it is necessary to propose an improved technical means to solve this problem.

[0004] In view of the prior art, there is a problem that the prior art cannot test a non-border scan wafer by boundary scan, and the present invention discloses a system and method for testing a non-border scan wafer and its peripheral lines based on boundary scan, wherein: 0005] A system for testing a non-border scan wafer and its peripheral lines based on boundary scan, comprising: at least one Boundary Scan wafer and at least one boundary scan wafer. [0006] The non-border scan chip includes at least one chip driving pin, at least one first data output pin, and at least one first data input pin. [0007] The boundary scan chip further includes at least one control pin, at least one second data output pin, and at least one second data input pin; the control pin is electrically connected to the chip driving pin, and is configured by a boundary scan technology. The chip driving pin position; the second data output pin is electrically connected to the first data input pin, and the input data of the first data input pin is set by the boundary scan technology; the second data input pin and the first data output pin Electrical connection for reading the output data of the first data output pin. [0008] wherein, the control pin sets the chip driving pin through the boundary scan technology, the second data output pin sets the input data of the first data input pin through the boundary scan technology, and the second data input pin reads the first data. The output data of the output pin is used to simulate the working timing of the non-border scan chip, and the boundary scan chip determines whether the output data of the first data output pin matches the preset data: [0009] When the output data of the first data output pin is When the preset data matches, the non-border scan wafer passes the test to be in a normal working state and the connection state between the non-border scan wafer and the boundary scan wafer pin is normal; [0010] when the output data of the first data output pin is When the preset data does not match, the non-border scan wafer fails to pass the test, that is, the abnormal working state or the connection state between the non-border scan wafer and the boundary scan wafer pin is abnormal. [0011] The method for testing a non-border scan wafer and its peripheral lines based on boundary scan according to the present invention comprises the following steps: [0012] First, at least one Boundary Scan wafer is provided, and the non-border scan wafer includes At least one chip driving pin, at least one first data output pin, and at least one first data input pin; then, providing at least one boundary scan chip, including at least one control pin, at least one second data output pin, and At least one second data input pin; then, the control pin is electrically connected to the chip drive pin, and the chip drive pin is set by the boundary scan technology; then, the second data output pin and the first data input pin are electrically Sexual connection, the boundary data scanning technology is used to set the input data of the first data input pin; then, the second data input pin is electrically connected with the first data output pin to read the output of the first data output pin Data; then, the boundary scan chip determines whether the output data of the first data output pin is associated with the preset data Then, when the output data of the first data output pin matches the preset data, the non-border scan wafer passes the test to be in a normal working state and the connection state between the non-boundary scan chip and the boundary scan chip pin is normal; Finally, when the output data of the first data output pin does not match the preset data, the non-border scan wafer fails to pass the test, that is, the abnormal working state or the connection between the non-border scan chip and the boundary scan chip pin is An abnormality; wherein the control pin sets the chip driving pin through the boundary scan technology, the second data output pin sets the input data of the first data input pin through the boundary scan technology, and the second data input pin reads the first data output. The output data of the pin is used to simulate the operational timing of the non-border scan wafer. [0013] The system and method disclosed by the present invention are as above, and the difference from the prior art is that the boundary timing of the non-border scan wafer is simulated by the boundary scan wafer to drive the non-border scan wafer, and the boundary scan wafer determines the output of the non-border scan wafer. When the data is consistent with the preset data, the non-border scan wafer passes the test to be in a normal working state and the connection state between the non-border scan wafer and the boundary scan wafer pin is normal; the boundary scan wafer judges the output data and the pre-border scan wafer output data. When the data is inconsistent, the non-border scan wafer passes the test to be in an abnormal working state and the connection state between the non-border scan wafer and the boundary scan wafer pin is abnormal. [0014] Through the above technical means, the present invention can achieve the technical effect of testing the non-boundary scan wafer and its peripheral lines based on boundary scan.

[0016] The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, and the implementation of the present invention to solve the technical problems and achieve the technical effects can be fully understood and implemented. [0017] Hereinafter, the system for testing a non-border scan chip and its peripheral lines based on boundary scan according to the present invention will be described first, and please refer to FIG. 1 and FIG. 1 is a boundary based on the present invention. A system block diagram of the test non-border scan wafer and its surrounding circuitry is scanned. [0018] A system for testing a non-boundary scan wafer and its peripheral lines based on boundary scan disclosed in the present invention includes: at least one non-boundary scan wafer 10 and at least one boundary scan wafer 20. [0019] The Boundary Scan wafer 10 is a chip that does not conform to the Joint Test Action Group (JTAG) specification, that is, a chip that does not support boundary scan technology, for example, a shift register. (Shift register), logic gate, etc., are merely illustrative here, and are not intended to limit the scope of application of the present invention. [0020] The non-boundary scan wafer 10 includes at least one wafer drive pin 11, at least one first data output pin 12, and at least one first data input pin 13, and the wafer drive pin 11 of the non-boundary scan wafer 10 is, for example, : clock (CLK) pin, shift (SHFTLD) pin, etc., are for illustrative purposes only, and are not limited to the application of the present invention, corresponding to different wafers, driving wafer drive of the wafer Pins 11 may be the same, may not be the same, or may be partially identical and partially different. [0021] The first data output pin 12 of the non-boundary scan chip 10 is a general data input pin and the first data input pin 13 is a general data output pin. [0022] The boundary scan wafer 20 is a wafer conforming to the joint test work group specification, that is, a wafer supporting the boundary scan technology, and the boundary scan wafer 20 includes at least one control pin 21 and at least a second data output pin 22 And at least one second data input pin 23, and the boundary scan technology can be used for the control pin 21, the second data output pin 22 and the second data input pin 23 of the boundary scan wafer 20. [0023] The control pin 21 of the boundary scan wafer 20 is electrically connected to the wafer drive pin 11 of the non-border scan wafer 10, and the control pin 21 of the boundary scan wafer 20 is provided with the wafer drive of the non-boundary scan wafer 10 by boundary scan technology. Pin 11. [0024] The second data output pin 22 of the boundary scan wafer 20 is electrically connected to the first data input pin 13 of the non-border scan wafer 10, and the second data output pin 22 of the boundary scan wafer 20 is set by the boundary scan technology. The input data of the first data input pin 13 of the non-boundary scan wafer 10. [0025] The second data input pin 23 of the boundary scan wafer 20 is electrically connected to the first data output pin 12 of the non-border scan wafer 10, and the second data input pin 23 of the boundary scan wafer 20 is used for reading non- The output data of the first data output pin 12 of the boundary scan wafer 10 is scanned. [0026] The control pin 21 of the boundary scan wafer 20 is configured to set the wafer drive pin 11 of the non-border scan wafer 10 and the second data output pin 22 of the boundary scan wafer 20 through the boundary scan technology to set the non-boundary scan through the boundary scan technology. The input data of the first data input pin 13 of the wafer 10 and the second data input pin 23 of the boundary scan wafer 20 read the output data of the first data output pin 12 of the non-border scan wafer 10 to simulate a non-border scan chip. 10 working sequence. [0027] Next, the boundary scan wafer 20 further determines whether the output data of the first data output pin 12 of the non-border scan wafer 10 matches the preset data. [0028] When the boundary scan wafer 20 determines that the output data of the first data output pin 12 of the non-border scan wafer 10 matches the preset data, the non-boundary scan wafer 10 passes the test for normal operation and the non-boundary scan wafer. The connection state between 10 and the boundary scan wafer 20 pin is normal. [0029] When the boundary scan wafer 20 determines that the output data of the first data output pin 12 of the non-border scan wafer 10 does not match the preset data, then the non-boundary scan wafer 10 fails to pass the test and is in an abnormal working state or The connection state between the non-border scan wafer 10 and the boundary scan wafer 20 pin is abnormal. [0030] It should be noted that the non-border scan wafer 10 and the boundary scan wafer 20 may be disposed on the same circuit board, and the non-border scan wafer 10 and the boundary scan wafer 20 may be disposed on different circuit boards or non-boundaries. The portions of the scan wafer 10 and the boundary scan wafer 20 may be disposed on the same circuit board, and the portions of the non-border scan wafer 10 and the boundary scan wafer 20 may be disposed on different circuit boards, which are merely illustrative and not This limitation is limited to the scope of application of the present invention. [0031] Next, the operation system and method of the first embodiment of the present invention will be described below with reference to the first embodiment, and reference is also made to "Fig. 1" and "Fig. 2", "Fig. 2 A flow chart of a method for testing a non-boundary scan wafer and its peripheral lines based on boundary scan is shown in the present invention. [0032] Please refer to FIG. 3, and FIG. 3 is a schematic diagram showing the test architecture of the first embodiment of the non-boundary scan chip and its peripheral lines based on the boundary scan test of the present invention. [0033] In the "Fig. 3", the non-border scan wafer 10 (8-bit shift register) is disposed on the first circuit board, and the first boundary scan wafer 201 is disposed on the second circuit board and the second boundary scan wafer. 202 is disposed on the third circuit board as an example. The present invention is not limited thereto. The first boundary scan chip 201 includes a first control pin N1, a second control pin N2, and a second data input pin N3 ( Step 102), the second boundary scan wafer 202 includes a second data output pin M1 and a second data output pin M2 (step 102). The non-boundary scan chip 10 includes a first chip driving pin CLK and a second chip. The drive pin SHFTLD, the first data output pin DATA_Q, the first data input pin G, and the first data input pin H (step 101). [0034] The first control pin N1 of the first boundary scan wafer 201 is electrically connected to the first chip driving pin CLK pin of the non-border scan wafer 10 (step 103), and the second control of the first boundary scan wafer 201 The pin position N2 is electrically connected to the second wafer driving pin SHFTLD of the non-border scan wafer 10 (step 103). [0035] The second data input pin N3 of the first boundary scan wafer 201 is electrically connected to the first data output pin DATA_Q of the non-border scan wafer 10 (step 105), and the second data output of the second boundary scan wafer 202 is performed. The pin M1 is electrically connected to the first data input pin G of the non-border scan wafer 10 (step 104), the second data output pin M2 of the second boundary scan wafer 202 and the first data input of the non-boundary scan wafer 10. Pin H is electrically connected (step 104). [0036] controlling the first control pin N1 and the second control pin N2 of the first boundary scan wafer 201 by the boundary scan technology to set the first chip drive pin CLK and the second die drive pin SHFTLD of the non-border scan wafer 10. (Step 103); controlling the second data output pin M1 and the second data output pin M2 of the second boundary scan wafer 202 by the boundary scan technique to set the first data input pin G of the non-border scan wafer 10 and the non-boundary scan The first data of the wafer 10 is input to the input data of the pin H (step 104), and the first data output pin DATA_Q of the non-border scan wafer 10 is read by the second data input pin N3 of the first boundary scan wafer 201. The data is output (step 105) to simulate the operational timing of the non-boundary scan wafer 10. [0037] In the first stage of the test, the boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled to be "1" by the boundary scan technique, and the second boundary scan wafer 202 is controlled by the boundary scan technique. The boundary value of the second data output pin M1 and the second data output pin M2 is set to "0", and the boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled by the boundary scan technique to be set to " 0", that is, the second wafer driving pin SHFTLD of the non-boundary scanning wafer 10 is set to "0" by "1", at this time, the non-boundary scanning wafer 10 simultaneously reads each of the first data input pins, and then The boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled to be "1" by the boundary scan technique to determine whether the output data of the first data output pin matches the preset data (step 106). . [0038] reading a boundary value of the second data input pin N3 of the first boundary scan wafer 201 by a boundary scan technique (in this case, reading a boundary value of the second data output pin M2 of the second boundary scan wafer 202) Assuming that the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is "0", then the non-boundary scan wafer 10 passes the first stage test (step 107); assuming the first boundary scan wafer 201 When the boundary value of the second data input pin N3 is not "0", the non-boundary scan wafer 10 does not pass the first stage test (step 108). [0039] Next, the boundary value of the first control pin N1 of the first boundary scan wafer 201 is controlled to be set to “0” and then set to “1” by the boundary scan technique, that is, the non-boundary scan wafer 10 A chip drive pin CLK is first set to "0" and then set to "1". [0040] reading a boundary value of the second data input pin N3 of the first boundary scan wafer 201 by a boundary scan technique (in this case, reading a boundary value of the second data output pin M1 of the second boundary scan wafer 202) Assuming that the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is "0", then the non-boundary scan wafer 10 passes the first stage test (step 107); assuming the first boundary scan wafer 201 When the boundary value of the second data input pin N3 is not "0", the non-boundary scan wafer 10 fails the first stage test (step 108). [0041] In the second stage test, the boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled to be "1" by the boundary scan technique, and the second boundary scan wafer 202 is controlled by the boundary scan technique. The boundary value of the second data output pin M1 and the second data output pin M2 is set to "1", and the boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled by the boundary scan technique to be set to " 0", that is, the second wafer driving pin SHFTLD of the non-boundary scanning wafer 10 is set to "0" by "1", at this time, the non-boundary scanning wafer 10 simultaneously reads each of the first data input pins, and then The boundary value of the second control pin N2 of the first boundary scan wafer 201 is controlled to be "1" by the boundary scan technique. [0042] reading the boundary value of the second data input pin N3 of the first boundary scan wafer 201 by the boundary scan technology (in this case, reading the boundary value of the second data output pin M2 of the second boundary scan wafer 202) Assuming that the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is "1", the non-boundary scan wafer 10 passes the second stage test (step 107); assuming the first boundary scan wafer 201 When the boundary value of the second data input pin N3 is not "1", the non-boundary scan wafer 10 does not pass the second stage test (step 108). [0043] Next, the boundary value of the first control pin N1 of the first boundary scan wafer 201 is controlled to be set to “0” and then set to “1” by the boundary scan technique, that is, the non-boundary scan wafer 10 A chip drive pin CLK is first set to "0" and then set to "1". [0044] reading a boundary value of the second data input pin N3 of the first boundary scan wafer 201 by using a boundary scan technique (in this case, reading a boundary value of the second data output pin M1 of the second boundary scan wafer 202) Assuming that the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is "1", the non-boundary scan wafer 10 passes the second stage test (step 107); assuming the first boundary scan wafer 201 When the boundary value of the second data input pin N3 is not "1", the non-boundary scan wafer 10 does not pass the second stage test (step 108). [0045] After the testing of the first phase and the second phase is completed, the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is the same as the second data output pin M1 of the second boundary scan wafer 202. When the boundary value and the boundary value of the second data output pin M1 of the second boundary scan wafer 202 are the same, the non-boundary scan wafer 10 is in a normal working state and the non-boundary scan wafer 10 is connected to the boundary of the boundary scan wafer 20. The line state is normal (step 107); the boundary value of the second data input pin N3 of the first boundary scan wafer 201 and the boundary value of the second data output pin M1 of the second boundary scan wafer 202 and the second boundary scan wafer When the boundary value of the second data output pin M1 of 202 is different, the non-boundary scan wafer 10 is in an abnormal working state or the non-boundary scan wafer 10 and the first boundary scan wafer 201 or the second boundary scan wafer 202. The connection state between the pins is abnormal (step 108). [0046] Please refer to FIG. 4, and FIG. 4 is a schematic diagram showing the test architecture of the second embodiment of the non-boundary scan chip and its peripheral lines based on the boundary scan test of the present invention. [0047] In the "figure 4", the first non-boundary scan wafer 101 (shift register), the second non-boundary scan wafer 102 (logic gate AND), and the third non-boundary scan wafer 103 (logic gate) The first circuit board is disposed on the first circuit board, the first boundary scan wafer 201 is disposed on the second circuit board, and the second boundary scan wafer 202 is disposed on the third circuit board. The present invention is not limited thereto. The boundary scan chip 101 includes a first chip driving pin CLK, a second chip driving pin SHFTLD, a first data output pin DATA_Q, a first data input pin G, and a first data input pin H (step 101). The second non-boundary scan chip 102 includes a first data input pin W and a first data input pin X (step 101). The third non-boundary scan chip 103 includes a first data input pin Y and a first data input. The position Z (step 101), the first boundary scan wafer 201 includes a first control pin N1, a second control pin N2, and a second data input pin N3 (step 102). The second boundary scan wafer 202 includes Second data A pin M1, the second data output pin M2, M3 of the second data output pin and a second data output pin M4 (step 102). The first control pin N1 of the first boundary scan wafer 201 is electrically connected to the first chip driving pin CLK pin of the first non-boundary scanning chip 101 (step 103), and the first boundary scan wafer 201 is The second control pin N2 is electrically connected to the second die drive pin SHFTLD of the first non-border scan wafer 101 (step 103). [0049] The second data input pin N3 of the first boundary scan wafer 201 is electrically connected to the first data output pin DATA_Q of the first non-border scan wafer 101 (step 105), and the second boundary scan chip 202 is second. The data output pin M1 is electrically connected to the first data input pin W of the second non-border scan wafer 102 (step 104), the second data output pin M2 of the second boundary scan wafer 202 and the second non-boundary scan chip. The first data input pin X of the 102 is electrically connected (step 104), and the second data output pin M3 of the second boundary scan wafer 202 is electrically connected to the first data input pin Y of the third non-boundary scan wafer 103. (Step 104), the second data output pin M4 of the second boundary scan wafer 202 is electrically connected to the first data input pin Z of the third non-border scan wafer 103 (step 104). [0050] The process of testing (ie, step 103 to step 106) may refer to the description of the first embodiment, and the difference between the second embodiment and the first embodiment is that eight stages of testing are required: [0051] And the second stage of the test is to control the boundary value of the second data output pin M1 of the second boundary scan wafer 202 to be set to “0” by the boundary scan technique, and set the boundary value of the second data output pin M2 to “0”. The boundary value of the second data output pin M3 is set to "0" and the boundary value of the second data output pin M4 is set to "0". [0052] reading a boundary value of the second data input pin N3 of the first boundary scan wafer 201 by a boundary scan technique (the first stage is reading the second data output pin M3 of the second boundary scan wafer 202 and the first The logical operation result of the boundary value of the data output pin M4 is the logical operation result of reading the boundary value of the second data output pin M1 of the second boundary scan chip 202 and the second data output pin M2. [0053] The third stage and the fourth stage test are to control the boundary value of the second data output pin M1 of the second boundary scan wafer 202 to be set to "0" and the boundary of the second data output pin M2 by the boundary scan technique. The value is set to "1", the boundary value of the second data output pin M3 is set to "0", and the boundary value of the second data output pin M4 is set to "1". [0054] reading the boundary value of the second data input pin N3 of the first boundary scan wafer 201 through the boundary scan technology (the third stage is reading the second data output pin M3 of the second boundary scan wafer 202 and the first The logical operation result of the boundary value of the data output pin M4 is the logical operation result of reading the boundary value of the second data output pin M1 and the second data output pin M2 of the second boundary scan chip 202). [0055] The fifth stage and the sixth stage test are to control the boundary value of the second data output pin M1 of the second boundary scan wafer 202 to be set to "1" and the boundary of the second data output pin M2 by the boundary scan technique. The value is set to "0", the boundary value of the second data output pin M3 is set to "1", and the boundary value of the second data output pin M4 is set to "0". [0056] reading the boundary value of the second data input pin N3 of the first boundary scan wafer 201 through the boundary scan technology (the fifth stage is reading the second data output pin M3 of the second boundary scan wafer 202 and the first The logical operation result of the boundary value of the data output pin M4 is the logical operation result of reading the boundary value of the second data output pin M1 of the second boundary scan chip 202 and the second data output pin M2. [0057] The test of the seventh stage and the eighth stage is to control the boundary value of the second data output pin M1 of the second boundary scan wafer 202 to be set to "1" and the boundary of the second data output pin M2 by the boundary scan technique. The value is set to "1", the boundary value of the second data output pin M3 is set to "1", and the boundary value of the second data output pin M4 is set to "1". [0058] reading the boundary value of the second data input pin N3 of the first boundary scan wafer 201 through the boundary scan technology (the seventh stage is reading the second data output pin M3 of the second boundary scan wafer 202 and the first The logical operation result of the boundary value of the data output pin M4 is the logical operation result of reading the boundary value of the second data output pin M1 and the second data output pin M2 of the second boundary scan chip 202). [0059] After the testing of the first stage to the eighth stage is completed, the boundary value of the second data input pin N3 of the first boundary scan wafer 201 and the second data output pin M3 of the second boundary scan wafer 202 and When the logical operation result of the boundary value of the second data output pin M4 and the logical operation result of the boundary value of the second data output pin M1 and the second data output pin M2 of the second boundary scan wafer 202 are the same, the non-boundary scan chip 10 is a normal working state and the connection state between the non-border scan wafer 10 and the boundary scan wafer 20 pin is normal (step 107); the boundary value of the second data input pin N3 of the first boundary scan wafer 201 is the second The logical operation result of the boundary value of the second data output pin M3 and the second data output pin M4 of the boundary scan wafer 202 and the second data output pin M1 and the second data output pin M2 boundary of the second boundary scan wafer 202 If the logical operation result of the value has a different result, the non-boundary scan wafer 10 is in an abnormal working state or between the non-boundary scan wafer 10 and the boundary scan wafer 20 pin. Line status is abnormal (step 108). [0060] In summary, it can be seen that the difference between the present invention and the prior art is that the boundary timing of the non-border scan wafer is simulated by the boundary scan wafer to drive the non-border scan wafer, and the boundary scan wafer determines the output data of the non-border scan wafer. When the preset data matches, the non-border scan wafer passes the test to be in a normal working state and the connection state between the non-border scan wafer and the boundary scan wafer pin is normal; the boundary scan wafer judges the output data and the preset data of the non-border scan wafer. When there is no match, the non-border scan wafer passes the test to an abnormal operating state and the connection state between the non-border scan wafer and the boundary scan wafer pin is abnormal. [0061] The technical problem of the prior art that the prior art cannot test the non-boundary scan wafer by boundary scan can be solved by the prior art, thereby achieving the technical effect of testing the non-boundary scan wafer and its peripheral lines based on the boundary scan. [0062] Although the embodiments of the present invention are as described above, the above description is not intended to directly limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

[0063]
10‧‧‧Non-boundary scanning wafer
101‧‧‧First non-boundary scanning wafer
102‧‧‧Second non-border scan wafer
103‧‧‧ Third non-boundary scanning wafer
11‧‧‧ Chip drive pin
12‧‧‧First data output pin
13‧‧‧First data input pin
20‧‧‧Boundary Scan Wafer
201‧‧‧First boundary scan wafer
202‧‧‧Second boundary scan wafer
21‧‧‧Control feet
22‧‧‧Second data output pin
23‧‧‧Second data input pin
CLK‧‧‧First chip drive pin
N1‧‧‧First control pin
N2‧‧‧second control pin
N3‧‧‧Second data input pin
M1‧‧‧Second data output pin
M2‧‧‧Second data output pin
M3‧‧‧Second data output pin
M4‧‧‧Second data output pin
SHFTLD second chip drive pin
DATA_Q first data output pin
G‧‧‧First data input pin
H‧‧‧First data input pin
W‧‧‧First data input pin
X‧‧‧First data input pin
Y‧‧‧First data input pin
Z‧‧‧First data input pin step 101‧‧‧ provides at least one non-border scan chip, the non-border scan chip includes at least one chip drive pin, at least one first data output pin and at least one first data input The foot step 102‧‧‧ provides at least one boundary scan chip, including at least one control pin, at least one second data output pin, and at least one second data input pin. Step 103‧‧‧ Control pin and chip drive pin The bit is electrically connected, and the chip driving pin is set by the boundary scan technology. Step 104‧‧ The second data output pin is electrically connected to the first data input pin, and the input of the first data input pin is set by the boundary scan technology. Data step 105‧‧‧ The second data input pin is electrically connected to the first data output pin to read the output data of the first data output pin. Step 106‧‧‧ Boundary scan chip determines the first data output pin Whether the output data of the bit matches the preset data. Step 107‧‧‧ When the output data of the first data output pin matches the preset data, the non-boundary scan chip Passing the test to normal operation and the connection state between the non-border scan wafer and the boundary scan wafer pin is normal. Step 108‧‧‧ When the output data of the first data output pin does not match the preset data, the non-boundary If the scan wafer fails the test, it is abnormal operation or the connection between the non-border scan wafer and the boundary scan wafer pin is abnormal.

[0015] FIG. 1 is a block diagram of a system for testing a non-border scan wafer and its peripheral lines based on boundary scan according to the present invention. FIG. 2 is a flow chart showing a method for testing a non-boundary scan wafer and its peripheral lines based on boundary scan according to the present invention. FIG. 3 is a schematic diagram showing the test architecture of the first embodiment of the non-boundary scan chip and its peripheral lines based on the boundary scan test of the present invention. FIG. 4 is a schematic diagram showing the test architecture of the second embodiment of the non-boundary scan chip and its peripheral lines based on the boundary scan test of the present invention.

10‧‧‧Non-boundary scanning wafer

11‧‧‧ Chip drive pin

12‧‧‧First data output pin

13‧‧‧First data input pin

20‧‧‧Boundary Scan Wafer

21‧‧‧Control feet

22‧‧‧Second data output pin

23‧‧‧Second data input pin

Claims (8)

A system for testing a non-border scan wafer and its peripheral lines based on boundary scan, comprising: at least one Boundary Scan wafer, including at least one wafer drive pin, at least one first data output pin, and at least one a data input pin; and at least one boundary scan chip, the boundary scan chip further includes: at least one control pin, the control pin is electrically connected to the chip driving pin, and is configured by a boundary scan technology a chip driving pin; at least one second data output pin, the second data output pin is electrically connected to the first data input pin, and the first data input pin is set by a boundary scan technology Input data; and at least one second data input pin, the second data input pin is electrically connected to the first data output pin for reading the output data of the first data output pin; Wherein, the control pin sets the chip driving pin through a boundary scan technology, and the second data output pin sets the first data input through a boundary scan technology Input data of the foot and the output data of the second data input pin to read the output data of the first data output pin to simulate the working sequence of the non-border scan chip, and the boundary scan chip determines the first data Whether the output data of the output pin matches the preset data: When the output data of the first data output pin matches the preset data, the non-boundary scan wafer passes the test to be in a normal working state and the non-boundary scan wafer and the boundary scan wafer pin are The inter-connected state is normal; and when the output data of the first data output pin does not match the preset data, the non-boundary scan chip fails to pass the test, that is, the abnormal working state or the The connection state between the non-border scan wafer and the boundary scan wafer pin is abnormal. The system for testing a non-border scan chip and its peripheral lines based on boundary scan according to claim 1, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin is electrically connected to the first data output pin, respectively, and can be electrically connected by different boundary scan chips. The system for testing a non-border scan chip and its peripheral lines based on boundary scan according to claim 1, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin is electrically connected to the first data output pin to be electrically connected by the same boundary scan chip. The system for testing a non-border scan chip and its peripheral lines based on boundary scan according to claim 1, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin and the first data output pin are electrically connected to each other by the same boundary scan chip. The connection, the non-the control pin, the non-the second data output pin, and the pin portion other than the second data input pin may be electrically connected by the different boundary scan wafers, respectively. A method for testing a non-border scan wafer and its peripheral lines based on boundary scan, comprising the steps of: providing at least one Boundary Scan wafer, the non-boundary scan wafer comprising at least one wafer drive pin, at least one a data output pin and at least one first data input pin; providing at least one boundary scan chip, the at least one control pin, the at least one second data output pin, and the at least one second data input pin; The control pin is electrically connected to the chip driving pin, and the chip driving pin is set by a boundary scan technology; the second data output pin is electrically connected to the first data input pin, The boundary scan technology sets the input data of the first data input pin; the second data input pin is electrically connected to the first data output pin for reading the first data output pin Outputting data; the boundary scan chip determines whether the output data of the first data output pin is consistent with a preset data; when the first data output pin When the output data matches the preset data, the non-boundary scan wafer passes the test to be in a normal working state and the connection state between the non-boundary scan wafer and the boundary scan wafer pin is normal; When the output data of the first data output pin does not match the preset data, the non-boundary scan chip fails to pass the test and is abnormally operated or The connection between the non-border scan chip and the boundary scan chip pin is abnormal; wherein the control pin sets the chip drive pin and the second data output pin through the boundary scan technology The boundary scan technique sets an input data of the first data input pin and the second data input pin reads an output data of the first data output pin to simulate an operation timing of the non-boundary scan chip. The method for testing a non-border scan chip and its peripheral lines based on a boundary scan according to claim 5, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin is electrically connected to the first data output pin, respectively, and can be electrically connected by different boundary scan chips. The method for testing a non-border scan chip and its peripheral lines based on a boundary scan according to claim 5, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin is electrically connected to the first data output pin to be electrically connected by the same boundary scan chip. The method for testing a non-border scan chip and its peripheral lines based on a boundary scan according to claim 5, wherein the control pin is electrically connected to the chip driving pin, and the second data output pin is The first data input pin is electrically connected to the first data input pin, and the second data input pin and the first data output pin are electrically connected to each other by the same boundary scan chip. The connection, the non-the control pin, the non-the second data output pin, and the pin portion other than the second data input pin may be electrically connected by the different boundary scan wafers, respectively.