JPH05114639A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which is capable of carrying out a functional differential operation test and a burn-in test with high efficiency by means of a simple device. CONSTITUTION:A semiconductor integrated circuit formed on a wafer comprises a function circuit section 11 which embodies its original functions, a function differential test circuit 12 and a burn-in circuit 13. The function differential test circuit 12 and the burn-in circuit section 13 include memories which house commands to be executed during the function differential testing and burn-in testing and memories which house the execution results respectively. It is possible to change over the operation mode of the semiconductor integrated circuit by changing a signal level to be applied to mode setting terminals T1 and T2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been dramatically improved in functionality and integration, and several million transistors have been formed on one chip. In order to inspect the function of such a high-performance and high-speed semiconductor integrated circuit, a functional operation test using a test device having a performance superior to those of the semiconductor integrated circuit is performed at the time of shipping of the product. The test pattern required for this test is created for each test device within a short period of time, and a simulation device required for these is newly introduced as the function of the semiconductor integrated circuit is improved.

[0003]

As described above, it is necessary to improve the function of the test apparatus used for the functional inspection in accordance with the semiconductor integrated circuit which is becoming more and more sophisticated year by year. Therefore, the mass production of the semiconductor integrated circuit is required. The investment in the test equipment invested in the project is increasing year by year.

Further, in addition to the functional operation test, in order to eliminate the initial failure of the semiconductor integrated circuit, an energization test under high temperature, that is, a screening called burn-in is carried out as a final inspection before shipment. In order to perform the above, it is necessary to prepare a burn-in board on which an IC socket is mounted, a jig such as a socket, a connector, and a device for supplying power and signals to the burn-in board for each model of semiconductor integrated circuit to be manufactured. It is a factor that increases the production cost.

The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit which enables a functional operation test and burn-in to be carried out at a low cost using an extremely simple apparatus as compared with the conventional one. It is in.

[0006]

The above object of the present invention is a semiconductor integrated circuit formed on a wafer, and a first instruction code to be executed for inspecting the function of the semiconductor integrated circuit. A functional operation test circuit section having a memory for storing and a memory for storing an execution result of the first instruction code; a memory for storing a second instruction code to be executed at the time of burn-in of the semiconductor integrated circuit; And a burn-in circuit section having a memory for storing the execution result of the instruction code of No. 2, and a semiconductor integrated circuit.

[0007]

When the semiconductor integrated circuit is formed on the wafer, the functional operation test and burn-in are performed using the functional operation test circuit section and the burn-in circuit section in the wafer state. The results of these tests are stored in memories in the functional operation test circuit section and the burn-in circuit section, respectively. The contents of these memories are read by an external tester to determine the quality of the semiconductor integrated circuit.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. In FIG. 2, reference numeral 10 denotes a semiconductor wafer, on which a large number of semiconductor integrated circuit chips according to the present invention are formed.

FIG. 2 is an enlarged view of the hatched portion of FIG. As shown in the figure, this semiconductor integrated circuit chip has a functional circuit unit 1 that realizes the original functions of the semiconductor integrated circuit.
1, a functional operation test circuit section 12 added to perform a functional operation test on the functional circuit section 11, and a burn-in circuit section 13 added to perform a burn-in.

The functional operation test circuit section 12 and the burn-in circuit section 13 respectively include a memory for storing an instruction code to be executed and a memory for storing an execution result of the instruction code. As shown in Table 1, the operation mode of the semiconductor integrated circuit is determined according to the level of the signal applied to the mode setting terminals T1 and T2.

[0011]

[Table 1]

Next, the procedure for carrying out the functional operation test and burn-in of the semiconductor integrated circuit will be described with reference to the flowchart of FIG.

First, in step S1, the mode setting terminal T
The functional operation test execution mode is selected by applying signals of levels "1" and "0" to 1 and T2, respectively. When signals such as power supply and clock are supplied from the outside, step S2
At, the instruction code is read from the memory in the functional operation test circuit section and executed. When the functional operation test is completed, in step S3, this result (the operation result when the semiconductor integrated circuit is an arithmetic circuit such as a CPU, and the sum check when the semiconductor integrated circuit is a memory) is stored in the memory in the functional operation test circuit section. To store. Next, in step S4, the burn-in execution mode is set by applying signals of levels "0" and "1" to the mode setting terminals T1 and T2, respectively. In step S5, the instruction code is read from the memory of the burn-in circuit section and executed. The result of this execution is step S6.
Is stored in the memory in the burn-in circuit, and the test ends.

After that, the test results stored in the memories of the functional operation test circuit section and the burn-in circuit section are read by an external test apparatus with the state of being formed on the wafer, and these are correct. Determine if there is. The external test apparatus does not have to be a conventional large-scale apparatus having a high function, but may be a simple apparatus having only a function of judging a test result.

If the result of the determination is that the semiconductor integrated circuit has a defect, it is removed in the wafer state and the process proceeds to the assembly process. Therefore, the cost required for the assembly is reduced as compared with the case of performing the burn-in after the conventional assembly. As for the semiconductor integrated circuit judged to be non-defective as a result of the judgment,
By assembling by dicing only the functional circuit section, it is possible to prevent an increase in assembly cost.

If the memory for storing the test results of the circuit and the burn-in circuit is a non-volatile memory such as PROM or EPROM, it is necessary to carry out the functional operation test and the burn-in and the judgment of the test result as a continuous process. Therefore, the test result can be determined at any time.

Further, if only one set of the functional operation test circuit and the burn-in circuit is provided per wafer, and all the functional circuits on the wafer are tested, the increase of the wafer area can be minimized. You can hold it down.

[0018]

The semiconductor integrated circuit formed on the wafer of the present invention includes a memory for storing a first instruction code to be executed to test the function of the semiconductor integrated circuit, and the first memory.
A self-test circuit section having a memory for storing the execution result of the instruction code, a memory for storing a second instruction code to be executed at the time of burn-in of the semiconductor integrated circuit, and an execution result of the second instruction code. Since a burn-in circuit unit having a memory for storing is provided on the same wafer, a very large number of semiconductor integrated circuits (for example, wafer lot units) can be functionally differentiated in a wafer state by using a simple device. Testing and burn-in can be performed simultaneously. Therefore, a large-scale and highly functional test device is not required, and jigs such as IC sockets and burn-in boards can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 2 is a view showing a wafer on which a semiconductor integrated circuit of the present invention is formed.

FIG. 3 is a flowchart for explaining a procedure for performing a functional differential test and burn-in of the semiconductor integrated circuit of FIG.

[Explanation of symbols]

 10 Semiconductor Integrated Circuit Wafer 11 Functional Circuit Section 12 Functional Differential Test Circuit Section 13 Burn-In Circuit Section T1, T2 Mode Setting Terminal

Claims (1)

[Claims] 1. A semiconductor integrated circuit formed on a wafer, the memory storing a first instruction code to be executed to test the function of the semiconductor integrated circuit, and the first memory.
Functional operation test circuit section having a memory for storing the execution result of the second instruction code, a memory for storing a second instruction code to be executed at the time of burn-in of the semiconductor integrated circuit, and an execution result of the second instruction code. And a burn-in circuit section having a memory for storing the semiconductor integrated circuit on the wafer.