JP4137082B2 - Semiconductor device testing equipment - Google Patents

Description

  The present invention relates to a test apparatus and test method for a semiconductor device, and more particularly to a test apparatus and test method for testing a semiconductor device having a large number of signal terminals for inputting / outputting various types of signals. is there.

  In recent years, with the increase in integration and mounting of LSI chips, the number of pins of semiconductor devices has increased, and the number of terminals has reached several hundred pins, sometimes exceeding 1,000 pins. For example, as shown in FIG. 1A, a ball grid array (BGA) in which, for example, solder balls 30 are arranged in a matrix on a mounting surface 1a of a semiconductor device (hereinafter, also simply referred to as “IC”) 1. In the type of IC, a solder ball 30, that is, a terminal having more than 500 pins, for example, has been commercialized. Here, each solder ball 30 has a function as a power supply terminal 31 or an input / output signal terminal 32.

  Such a functional test in an IC is performed by mounting the IC on a test board and electrically connecting each signal terminal to a test signal supply terminal, but the number of signal terminals on the IC side is the test on the test board. Since the number of signal supply terminals is greatly exceeded, all the signal terminals cannot be tested with one test board. In particular, in a DC test (Direct Current Test) for confirming input / output characteristics and the like, an electrical contact is surely required for the terminal to be measured, which is a big problem.

  The above “DC test” is a general term for tests that measure phenomena that can be grasped by a direct current method. Important things are current measurement such as operation current, standby current, and substrate current, input / output terminal leak measurement, continuity There are tests and the like. Of these, the input / output terminal leak test and continuity test require direct contact with the terminals to be measured. If the number of test terminals exceeds the number that can be tested at once by the LSI tester, the test is divided into multiple tests. In fact, it is necessary to perform a plurality of measuring jigs and the like in order to test all the terminals. The DC test is an important test that is indispensable for the temporary test (PT) and the final test (FT), and is paired with the AC test. An example of an IC test method that solves the above problems will be described with reference to FIGS.

  Here, a test method of the circuit function of the IC 1 as shown in FIG. 1A, particularly a case where a plurality of ICs having the same function are continuously tested will be described with reference to the flowchart shown in FIG. . First, in step S21, as shown in FIG. 1B, the power supply terminal 31 and the input / output signal terminal 32 on the mounting surface 1a of the IC 1 are partitioned by boundary lines L1 and L2 (dotted lines in the drawing), for example. For convenience, an arbitrary number of regions R1 to R4 are defined. The number of various signal terminals included in each of these areas is set so as not to exceed the number of corresponding test signal supply terminals provided on the test board.

  These regions R1 to R4 are each handled as a test target region. Here, since each area | region R1-R4 is arbitrarily divided by the boundary lines L1 and L2, the arrangement | positioning and the kind of the signal terminal in each area | region differ for every area | region. Next, IC1 is mounted on a predetermined test board. Here, when the region to be tested is, for example, region R1, the test board is provided with test signal supply terminals and wirings corresponding to the arrangement and types of signal terminals provided in the region R1.

  Hereinafter, the mounting state of the IC on the test board will be described in detail with reference to FIG. FIG. 3 is a perspective view of the IC 1 shown in FIG. 1 mounted on the test boards 2a and 2b when viewed from the lower side of the test board. In addition, the same code | symbol is attached | subjected to the component equivalent to FIG. 1, and the description is abbreviate | omitted. In step S22, the area R1 shown in FIG. 1B among the areas divided and partitioned in step S21 is set as the test target area, and in step S22b, the test board 2a for the area R1 is mounted on the test apparatus. The As shown in FIG. 3A, the test board 2a is provided with a test signal supply terminal 33 according to the arrangement and type of the power supply terminal 31 and the input / output signal terminal 32 provided in the region R1. In step S24, the power supply terminal 31 and the input / output signal terminal 32 provided in the region R1 are connected to the test signal supply terminal 33 on the test board 2a by the wiring 34. In step S23, the test program for the region R1 is loaded prior to mounting the IC1 on the test board 2a.

  That is, according to the arrangement and type of signal terminals in the region R1, a test board dedicated to the region R1 in which wirings 34 for connecting the power supply terminals 31 and the input / output signal terminals 32 to the corresponding test signal supply terminals 33 are formed. 2a is used. Next, in step S25, based on the loaded test program for the region R1, a predetermined power supply current is input to the power supply terminal 31 via the test signal supply terminal 33 and the wiring 34, and an input signal or the like is input to the predetermined input. The voltage is applied to the output signal terminal 32, and the function test for the region R1 is performed. In step S26, the result of the function test in the region R1 is determined based on the output signal output from the predetermined input / output signal terminal 32. Here, the IC determined to have a defective function is excluded from the subsequent functional test as a defective product in step S27. On the other hand, the IC determined to have a good function is removed from the test board, and it is determined in step S28 whether or not all the ICs have been tested.

  If all the ICs have not been tested, the process returns to step S24, other untested ICs are mounted on the same test board 2a, and the function test is repeated according to steps S25 to S26. . On the other hand, when all the IC tests have been completed for the region R1, it is determined in step S29 whether or not the functional tests have been completed for all the regions R1 to R4.

  Here, when the test is completed for all the regions R1 to R4, the function test is terminated. On the other hand, when the test has not been completed for all the regions R1 to R4, the process returns to step S22, and as shown in FIG. 3B, for example, the region R2 is set as the next test target region. In step S22b, the test board 2b for the region R2 is mounted on the test apparatus instead of the test board 2a for the region R1, and an IC is mounted on the test board 2b for the region R2, and the power supply terminal 31 of the region R2 is installed. And the input / output signal terminal 32 are connected to the test signal supply terminal 33 by the wiring 34. Then, a function test similar to that in the region R1 is performed using the test program loaded for the region R2.

  As described above, a series of steps S22 to S28 is repeatedly performed on the region R1 to the region R4. As described above, in the function test of the conventional multi-pin IC, all the input / output terminals are tested by repeatedly performing the function test for each test target area. More specifically, in the prior art, since the signal terminals of the semiconductor device to be tested are divided into arbitrary areas, the arrangement and types of the signal terminals are different for each divided area. Therefore, a dedicated test board corresponding to each divided area has to be produced, and a dedicated test program corresponding to each area has to be created, which increases the test cost.

  Furthermore, since the test board and test program used in the test are different for each divided area, every time the test target area is changed, it is necessary to transfer to a different test board or load a different test program. In addition, there was a problem that the number of test processes increased.

  The present invention has been made to solve the above-described problems, and in a functional test of a semiconductor device having a large number of signal terminals, a test apparatus for a semiconductor device for realizing a reduction in the number of test steps and a test cost. And to provide a test method.

An object of the present invention, the mounting surface comprising a plurality of regions, a test apparatus for testing a semiconductor device and a package having a asymmetric shape, and a test board for mounting the semiconductor device, on said test board A plurality of button switches formed, wherein one of the plurality of button switches is disposed at a position to be pressed when the semiconductor device is placed on the test board, and is pressed by the semiconductor device. This is achieved by providing a test apparatus that outputs a signal for specifying a region to be tested among the plurality of regions .

  According to the above means of the present invention, it is possible to perform a function test of a semiconductor device using a common test board and a common test program. This eliminates the need to replace the test board or load a new test program in accordance with the test area when the test target area is changed. Thus, the quality of all signal terminals can be easily tested, and the number of test steps and test costs can be reduced.

  According to the present invention, it is possible to perform a function test more easily than before, and to significantly reduce the cost when performing the function test.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 4 is a diagram showing the arrangement of signal terminals on the mounting surface of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 4, on the mounting surface of the semiconductor device (IC) 1 according to the first embodiment, test state setting (Test Access Port; hereinafter also referred to as “TAP”) terminals 10 a and 10 b, power supply terminals ( VDD) 11a and 11b, power supply terminals (GND) 12a and 12b, signal input terminals 13a and 13b, and signal output terminals 14a and 14b.

  That is, as shown in FIG. 4, when the mounting surface of IC1 is divided into regions R1 and R2 by the boundary line L, the TAP terminal 10a, the power supply terminal (VDD) 11a, and the power supply terminal (GND) in the region R1 on the mounting surface. ) 12a, signal input terminal 13a, signal output terminal 14a are TAP terminal 10b, power supply terminal (VDD) 11b, power supply terminal (GND) 12b, signal input terminal 13b, signal output terminal 14b in region R2, With the center point 15 of the outer shape of the IC 1 as the center of rotation, the arrangement on the mounting surface matches when rotated 180 degrees, and the types of terminals at the same position also match. That is, the arrangement of the terminals on the mounting surface is 180 degrees rotationally symmetric with the outline center point 15 as the rotation center.

  Note that the TAP terminals 10a and 10b are terminals for inputting test state control signals. One TAP terminal 10a and 10b is provided in each of the areas R1 and R2. It is arranged so that it will be in the same position when it is rotated. Next, the configuration of the functional test circuit provided in the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 5, the semiconductor device according to the present embodiment is provided in each of the TAP terminals 10a and 10b, the TAP controller 20a, the scan circuit 23, and the regions R1 and R2, and is output from the scan circuit 23. Input / output terminals 22a and 22b to which a control signal is input are provided. The TAP controller 20a receives a signal TMS for controlling the test mode and a test clock signal TCK.

  The scan circuit 23 has flip-flop circuits 21a and 21b that hold and output signals for sequentially controlling the states of the input / output terminals 22a and 22b based on the clock signal from the TAP controller 20a. In an IC having such a test circuit, when a control signal for setting a test state is input to the TAP controller 20a via the TAP terminal 10a or TAP terminal 10b in the regions R1 and R2 to be tested, the test is performed. Only the test circuit on the target region side, for example, the region R1 side is activated, and the input / output terminals 22a are sequentially set to the test state by the flip-flop circuit 21a based on a predetermined reference clock, and the other non-test is performed. Each input / output terminal 22b in the target region R2 is set to a state in which no current path is generated between the internal circuit and the input circuit 22b, for example, a high impedance state.

  Also, the order of scan paths in which the test signal is applied to the internal circuit by the scan circuit 23 via the input / output terminals 22a and 22b is set to be the same in the two regions R1 and R2. FIG. 6 is a diagram more specifically showing a circuit for performing a function test by setting an arbitrary region on the mounting surface to a test state. As shown in FIG. 6, this circuit includes an input / output terminal 22a and a boundary scan register BRa corresponding to the region R1, and includes an input / output terminal 22b and a boundary scan register BRb corresponding to the region R2. . Further, a test control circuit 20b to which a signal TMS for controlling a test mode and a test clock signal TCK are input is provided, and a transfer gate TG1 is provided between the test control circuit 20b and the boundary scan register BRa. A transfer gate TG2 is provided between 20b and the boundary scan register BRb. Here, the transfer gate TG1 is controlled by a signal supplied to the TAP terminal 10a, and the transfer gate TG2 is controlled by a signal supplied to the TAP terminal 10b. In this circuit, a test signal and data (signal TDI) for a test are supplied from the test control circuit 20b to the boundary scan registers BRa and BRb. Here, for example, when the region R1 is a test target, a high level signal is supplied to the TAP terminal 10a, so that the transfer gate TG1 is turned on, and the signal TDI is transmitted to the boundary scan register BRa. As a result, the input / output terminals 22a provided in the region R1 are sequentially set to the test state, and a desired function test is performed. On the other hand, since a low level signal is supplied to the TAP terminal 10b at this time, the transfer gate TG2 is turned off, and the signal TDI is not transmitted to the boundary scan register BRb. Note that a signal TDO such as data output from the boundary scan register BRa is input to the test control circuit 20b.

  Next, a semiconductor device testing method according to the first embodiment of the present invention will be described with reference to the flowchart shown in FIG. In particular, a case where a plurality of ICs having the same function are successively tested will be described here. First, in step S11, a terminal group on the mounting surface of IC1 is partitioned by, for example, a boundary line L to define two regions R1 and R2. Here, the number of terminals in each of the regions R1 and R2 does not exceed the number of test terminals provided on the test board for each type.

  Next, in step S12, a test program is loaded, and in step S13, a test target area is set. In step S14, IC1 is mounted on the test board. Here, regardless of the area to be tested, the terminals on the mounting surface are arranged in a rotationally symmetrical manner, so one type of test board is used regardless of which area is to be tested. With only one test program, the function test in step S15 can be performed for all terminals.

  Hereinafter, the mounting state of the IC on the test board will be described in detail with reference to FIG. FIG. 8 is a perspective view of the IC 1 mounted on the test board 2 as viewed from the back side of the test board 2. As shown in FIG. 8A, when the region R1 is set as the test target region, the semiconductor device 1 is mounted on the test board 2 with the region R1 side shown in FIG. . And each terminal provided in area | region R1 is connected to the corresponding test terminal 16 on a test board by the wiring 17. FIG.

  Next, in step S15, based on the loaded test program common to all regions, for example, a predetermined power supply current is applied to the power supply terminal (VDD) 11a, and an input signal is applied to the signal input terminal 13a. Applied. In step S16, the function of the region R1 is determined based on the signal output from the signal output terminal 14a. In this determination, the IC determined to be defective is excluded from the subsequent functional test as a defective product in step S17.

  Next, the IC 1 that has been the test target is removed from the test board 2, the next untested IC is mounted on the same test board 2, and the functional test according to steps S 14 to S 16 is repeated. If it is determined in step S18 that the functional test in the area R1 has been completed for all the ICs, the process returns to step S13, and as shown in FIG. Is set. Next, in step S14, the IC1 is mounted on the common test board 2 with the region R2 side upward in the drawing, that is, the IC1 is rotated 180 degrees. Then, various terminals in the region R2 are connected to the test terminal 16 by the wiring 17, and the same functional test as that in the region R1 is performed in step S15.

  In this way, when it is determined in step S19 that the functional test has been completed for all the regions R1 and R2, the functional test is terminated. As described above, according to the semiconductor device and the test method thereof according to the first embodiment, the signal terminals are provided on the mounting surface of the semiconductor device so as to be 180 degrees rotationally symmetric, and the inside of the semiconductor device is scanned. Since the circuit passes through the scan path in the same order for each area, even if the number of terminals provided in the IC exceeds the number of terminals on the test board, one common test Using the board and test program, a simple operation of changing the mounting angle of the semiconductor device to the test board by 180 degrees enables functional tests for all divided areas and DC tests for all input / output terminals. Costs can be greatly reduced. Further, the number of test steps can be reduced.

[Embodiment 2]
FIG. 9 is a diagram showing the arrangement of signal terminals on the mounting surface of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 9, the mounting surface of the semiconductor device (IC) 1 according to the second embodiment is divided into four regions RA to RD by boundary lines L1 and L2, and the region RA includes a test control terminal 9a and a power source. A terminal (VDD) 11a, a power supply terminal (GND) 12a, a signal input terminal 13a, and a signal output terminal 14a are provided.

  In addition, as with the mounting surface of the semiconductor device according to the first embodiment, these terminals are arranged on the mounting surface before and after the rotation when rotated 90 degrees around the outer shape center point 15 of the IC 1 as the rotation center. The types of terminals that match and are located at the same position are also provided. That is, the arrangement of the terminals on the mounting surface is rotationally symmetric by 90 degrees with the outline center point 15 as the rotation center.

  FIG. 10 is a diagram showing a configuration of the test board 2 on which the semiconductor device 1 shown in FIG. 9 is mounted. As shown in FIG. 10, the test board 2 is provided with a terminal 19b provided corresponding to each terminal provided on the mounting surface of the IC 1 and a connect terminal 18b connected to the test tester channel. Each terminal 19b is connected to the corresponding connection terminal 18b by a wiring 17b. Here, a test signal based on a test program is supplied from a test tester (not shown) to the connection terminal 18b, and a functional test is performed for each divided area.

[Embodiment 3]
However, the semiconductor device and the test method thereof according to the first or second embodiment have the following problems.

  First, since the semiconductor device according to the first or second embodiment can be sequentially rotated by a predetermined angle and mounted on a test board, all test areas can be examined with one test program. It cannot be distinguished which region the result is, and it cannot be determined whether or not the functional test has been performed for all the test regions. Secondly, since the terminals on the mounting surface are arranged so as to be rotationally symmetric with respect to the center point of the outer shape, there is a problem that a great restriction is imposed on the terminal arrangement at the time of chip design.

  Therefore, a semiconductor device and a test method for solving the first problem will be described in the third embodiment. FIG. 11 is a diagram showing the arrangement of signal terminals on the mounting surface of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 11, the mounting surface of the semiconductor device (IC) 1 according to the third embodiment is divided into regions RA to RD by boundary lines L1 and L2, and each region has a test control terminal 9a and a power supply terminal. (VDD) 11a, a power supply terminal (GND) 12a, a signal input terminal 13a, a signal output terminal 14a are provided, and an index terminal 5 is provided.

  The terminals in each region are provided so that the arrangement on the mounting surface matches when rotated 90 degrees with the outer shape center point 15 as the rotation center, and the types of terminals at the same position also match. Yes. That is, the arrangement of the terminals on the mounting surface is rotationally symmetric by 90 degrees with the outline center point 15 as the rotation center. Here, the index terminal 5 is a terminal for outputting an area identification signal for distinguishing a certain area from other areas, and is the same position when rotated 90 degrees around the outer shape center point 15 as the rotation center like the other terminals. Are arranged one by one in each of the regions RA to RD. Note that the area identification signal is for recognizing which area the result of the functional test of a divided area is.

  FIG. 12 is a diagram illustrating a configuration of the region identification signal generation circuit. As shown in FIG. 12, this circuit includes a power supply node ND and a resistor 11 </ b> C connected between the power supply node ND and the index terminal 5. Here, since the size of the resistor 11C varies from region to region, the voltage of the region identification signal output from the index terminal 5 varies from region to region. Accordingly, by measuring the voltage of the region identification signal, it is possible to identify which region the result of the obtained functional test is.

  FIG. 13 is a diagram showing a configuration of the test board 2 on which the semiconductor device 1 shown in FIG. 11 is mounted. As shown in FIG. 13, on the test board 2, terminals for obtaining electrical contacts corresponding to the terminals included in one area RA among the four areas RA to RD divided. 19b and a connection terminal 18 for connecting the test board 2 and a tester channel (not shown). The terminal 19b and the connection terminal 18 are connected by a wiring 17b.

  According to the semiconductor device according to the third embodiment, the same effect as that of the semiconductor device according to the first or second embodiment is obtained, but further, a function test is performed by the region identification signal output from the index terminal 5. Thus, it is possible to specify the area on the mounting surface that is the target of the test, and to determine whether or not the functional test has been performed in all the test areas.

[Embodiment 4]
On the mounting surface of the semiconductor device according to the third embodiment, as described above, the index terminal 5 is disposed at a rotationally symmetric position of 90 degrees with the outer shape center point 15 as a symmetric point. It is not necessary to be arranged at the position. Accordingly, a semiconductor device in which the index terminals 5 are arranged asymmetrically on the mounting surface will be described below.

  FIG. 14 is a diagram showing a terminal arrangement on the mounting surface of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 14, the terminals on the mounting surface of the semiconductor device according to the fourth embodiment are arranged so as to be rotationally symmetric as in the semiconductor device according to the third embodiment. The only difference is that the outer shape center point 15 is asymmetrically arranged. That is, the index terminals 5 are provided one by one in the plurality of regions RX at rotationally symmetric positions on the mounting surface, but the position in each region RX is freely determined for each of the regions RA to RD.

  FIG. 15 is a diagram showing a configuration of a test board on which the semiconductor device shown in FIG. 14 is mounted. FIG. 15 shows the case where the region RA of FIG. 14 is the test target. As shown in FIG. 15, this test board has the same configuration as the test board shown in FIG. 13, except that the four terminals 19b in the region RXB on the test board are short-circuited. . Therefore, according to such a test board, when the regions RA to RD on the mounting surface are sequentially tested by rotating and mounting the semiconductor device by 90 degrees, one index is provided for each region. If the terminal 5 is in electrical contact with any one of the four terminals 19b in the region RXB of the test board, a functional test according to the same test program can be realized for each region.

  The semiconductor device according to the fourth embodiment has the design freedom for the index terminal 5, but the semiconductor device with the design freedom for the other terminals can be considered in the same way. It is done. Further, in the semiconductor device according to the fourth embodiment, one existing terminal having a constant potential may be provided in the region RX instead of the index terminal 5 one by one. That is, as shown in FIG. 16, the signal output terminal 14a fixed at the high level is provided in the region RX in the region RA, the power supply terminal (VDD) 11a is provided in the region RX in the region RB, and the signal output terminal 14a in the region RC is provided. The region RX is provided with a signal output terminal 14a fixed at a low level, and the region RX in the region RD is provided with a power supply terminal (GND) 12a. Here, the voltage of the power supply terminal (VDD) 11a is 3.3V, the voltage of the signal output terminal 14a fixed at high level is 2.5V, the voltage of the signal output terminal 14a fixed at low level is 0.4V, and the power supply The voltage of the terminal (GND) 12a is 0V. Therefore, the region to be tested can be identified by reading the voltages of these terminals in the region RX during the function test.

  In addition to this, it is also conceivable to use a signal generated by a scan circuit or a frequency dividing circuit used for test control of a divided area for identification of the area. That is, for example, the signal SA generated by the existing frequency dividing circuit 24 shown in FIG. 17 is supplied to the terminal provided in the region RX in the region RA, and the signal SB is supplied to the terminal provided in the region RX in the region RB. Then, the signal SC is supplied to the terminal provided in the region RX in the region RC, and the signal SD is supplied to the terminal provided in the region RX in the region RD, whereby the region similar to the above can be identified.

  As described above, when a specific electrical signal is obtained for each area from a predetermined terminal of the test board when an arbitrary test area is tested, the area can be identified.

[Embodiment 5]
In the semiconductor device according to the above-described embodiment, by providing an index terminal having a predetermined voltage in the IC chip, the divided area can be identified. Instead of providing such a terminal, the IC chip It is also conceivable to identify the region by using the shape of the package.

  FIG. 18 is a diagram showing a configuration of a packaged semiconductor device according to the fifth embodiment of the present invention. As shown in FIG. 18, the package PKG of this semiconductor device has all other corners cut off, leaving only the corners close to the A region. FIG. 19 is a diagram showing a configuration of a test board on which the package PKG shown in FIG. 18 is mounted.

  As shown in FIG. 19, this test board has the same configuration as the test board shown in FIG. 13, but switches 51a are provided at the four corners of the package PKG to be mounted. In FIG. 20, the cross section Y1-Y2 is shown in FIG. 20, and the cross section X1-X2 is shown in FIG. Here, as shown in FIG. 20, the switch 51a at the corner close to the area A is turned on when the button switch BS is pushed from above by the package PKG, and the external input signal IN is connected to the test board connect terminal 18b. To be supplied to the A region. On the other hand, as shown in FIG. 21, the switch 51a at the corner close to the D region is not pushed from above because the package PKG is not placed on the button switch BS, so that the B region Alternatively, the switch 51a at the corner close to the C region is also in the off state.

  In this way, when only the switch 51a shown in FIG. 20 is turned on, the response to the external input signal IN in the A area is measured at a predetermined connection terminal, and the test area is identified as the A area. Will be made. Here, instead of supplying the external input signal IN from the outside, it may be considered to use a signal used inside the semiconductor device.

  Further, as shown in FIG. 18, the package PKG according to the fifth embodiment has three corners close to each of the B region, the C region, and the D region. Also by cutting out only one corner close to, it is possible to identify the test target region according to the position of the switch 51a turned off.

[Embodiment 6]
The semiconductor device according to the sixth embodiment of the present invention eliminates the second problem mentioned in the third embodiment, that is, the large limitation of terminal arrangement at the time of chip design due to the requirement of symmetry. FIG. 22 is a diagram showing a terminal arrangement on the mounting surface of the semiconductor device according to the sixth embodiment of the present invention.

  As shown in FIG. 22, the mounting surface is divided into a region RA and a region RB by a boundary line L. The number of terminals included in each region RA and RB is more than the number of terminals that can be simultaneously tested on the test board. There are few things. This division is set so that each of the areas RA and RB includes at least one index terminal 5 and one test control terminal 9a. Table 1 below shows the number of terminals arranged on the mounting surface of the semiconductor device shown in FIG.

表１に示されるように、信号の入力に関してはＡ領域で合計５つ、Ｂ領域で合計６つの端子が存在するが、いずれの領域についても試験ボードによる制限端子数の６以内とされている。以下、信号の出力と電源端子（ＶＤＤ及びＧＮＤ）についても同様であることがわかる。なお、図２２では領域ＲＡと領域ＲＢとはそれぞれ一続きの領域をなしているが、領域ＲＡまたは領域ＲＢは離散した複数の領域の集合からなるものであっても良い。

As shown in Table 1, there are a total of 5 terminals in the A area and 6 terminals in the B area in terms of signal input, but all areas are within 6 of the limit number of terminals by the test board. . Hereinafter, it is understood that the same applies to the signal output and the power supply terminals (VDD and GND). In FIG. 22, the region RA and the region RB each form a continuous region, but the region RA or the region RB may be composed of a set of a plurality of discrete regions.

  FIG. 23 is a diagram showing a configuration of a conventional A region test socket SA on which the semiconductor device shown in FIG. 22 is mounted, and FIG. 24 is a conventional B region on which the semiconductor device shown in FIG. 22 is mounted. It is a figure which shows the structure of test socket SB. As shown in FIG. 23 and FIG. 24, the A region and B region test sockets SA and SB each have terminals 63b and 63c for contacting the terminals on the mounting surface of the semiconductor device 1, and a test board (FIG. Terminals 64b and 64c for contact with each other (not shown), and the terminals 63b and 63c and the terminals 64b and 64c are connected by wirings 65b and 65c.

  Here, comparing FIG. 23 with FIG. 24, since the types of terminals of the semiconductor devices connected to the terminals 64b and 64c that contact the test board are different, a test program for functional test is performed on the A region and the B region. It is necessary to prepare each separately. On the other hand, FIG. 25 shows a configuration of the A region test socket SA according to Embodiment 6 of the present invention, and FIG. 26 is a diagram showing a configuration of the B region test socket SB.

  Here, the A-area test socket SA shown in FIG. 25 has the same configuration as the A-area test socket SA shown in FIG. 23, but is different in that a dummy terminal 66b is provided. This is because the number of terminals for inputting signals is smaller in the A area than in the B area, as shown in Table 1, so that the number is equal. Therefore, here, the signal input terminal 13a in the region RB is used as the dummy terminal 66b.

  Further, the B area test socket SB shown in FIG. 26 has the same configuration as the B area test socket SB shown in FIG. 24, but is different in that a dummy terminal 66c is provided. This is because the number of terminals for outputting signals and the number of power supply terminals (VDD) are smaller in the B region than in the A region, respectively, as shown in Table 1. Accordingly, here, the signal output terminal 14a and the power supply terminal (VDD) 11a in the region RA are used as the dummy terminal 66c.

  Thus, by providing dummy terminals in the A region test socket and the B region test socket, the types and arrangement of the terminals 64b and 64c that contact the test board on both sockets are the same. That is, the configuration when the conventional A region test socket shown in FIG. 23 is mounted on the test board is shown in FIG. 27, and the conventional B region test socket shown in FIG. 24 is mounted on the test board. FIG. 28 shows the configuration of the case, but it can be seen that the connection relationship between the test board 2 and the test tester channel (not shown) differs depending on the region to be tested. Therefore, conventionally, it is necessary to create a test socket for each divided area and also create a test program for each divided area.

  On the other hand, FIG. 29 is a diagram showing a configuration of the test board 2 on which the A area test socket SA shown in FIG. 25 or the B area test socket SB shown in FIG. 26 is mounted. As shown in FIG. 29, according to the test method according to the sixth embodiment, the test can be performed by simply changing the test socket, regardless of whether the A area is the test object or the B area. Since the connection relationship between the board 2 and the test tester channel can be maintained, the functional test can be performed for all the areas with one test program.

  Hereinafter, a test method according to Embodiment 6 of the present invention will be described with reference to the flowchart of FIG. First, in step S101, as shown in FIG. 22, each terminal on the mounting surface of the semiconductor device 1 is partitioned by, for example, a boundary line L to define regions A and B. Note that the number of terminals included in each of the regions A and B does not exceed the number of terminals provided on the test board.

  Next, in step S102, the test board is mounted on the test apparatus. Note that, regardless of whether the test object is the region A or the region B, the terminal of the socket to be in contact with the test board is invariable with respect to its arrangement and type as shown in FIGS. Functional tests can be performed with the same test program. Therefore, in step S103, a common test program is loaded into the area A and the area B in the test apparatus.

  Next, in step S104, an area to be tested is set. In the following, the case where the region A is first tested will be described. In this case, in step S105, the A region test socket SA shown in FIG. 25 is mounted on the test board as shown in FIG. In the next step S106, the semiconductor device is mounted on the test board via the socket SA. In this state, each terminal in area A is connected to a terminal on the test board.

  Here, in step S107, various signals such as a power supply voltage are supplied from the terminals on the test board to each terminal of the semiconductor device via the socket SA based on the test program, and a function test for the A region is performed. . In step S108, it is determined whether or not the semiconductor device is non-defective for the A region based on the signal output from the A region of the semiconductor device.

  As a result, when it is determined that the area A is defective, in step S109, the semiconductor device to be tested is excluded as a defective product from subsequent functional test targets. On the other hand, if it is determined that the area A is a non-defective product, it is determined in step S110 whether the functional test for all areas has been completed. Here, since the functional test of the B area is not yet completed, the process returns to step S104, the semiconductor device 1 is removed from the test board together with the socket SA, and a new area B is set as a test target.

  Next, in step S105, the B region test socket SB is mounted on the test board. In the same manner as in the case of the A region, the functional test is performed on the B region. Here, since the automatic mounting of the semiconductor device to the test board is generally performed by the automatic handler, the A area test socket SA is replaced with the B area test socket SB by the automatic handler.

  In this way, steps S104 to S110 are repeated until the functional test is completed for all the test target regions. If it is determined in step S110 that all the test areas have been tested, it is determined in step S111 whether or not a function test has been performed on all semiconductor devices, and untested semiconductor devices remain. In this case, the process proceeds to the next function test of the semiconductor device, and returns to step S104. On the other hand, if it is determined in step S111 that the function test has been completed for all semiconductor devices, the function test is terminated.

  In the above-described test method, after the functional test in all the test target regions is completed for a certain semiconductor device, the next functional test of the semiconductor device is performed for the first time. Therefore, if the socket replacement required every time a test for one test area is completed causes a time or cost burden, test using the method shown in the flowchart of FIG. Is also possible.

  That is, the test method shown in FIG. 31 is the same as the above-described test method up to step S208 for determining pass / fail for one region by the function test, but differs in the following points. If it is determined that the region in step S208 is non-defective, the semiconductor device is removed from the socket, and in step S210, it is determined whether or not the function test has been completed for all the semiconductor devices. If there is a semiconductor device, the process returns to step S206, and the next new semiconductor device is mounted in the same socket. In this way, by repeating steps S206 to S210 for all the semiconductor devices, the functional test is completed for one of a plurality of test target regions.

  Next, in step S211, it is determined whether or not the functional test for all areas has been completed. If an untested area remains, the process returns to step S204 to set a new test target area. As a result, the socket on the test board is replaced with the socket corresponding to the new test target area in step S205, and steps S206 to S210 are repeated for all semiconductor devices. In this way, when it is determined in step S211 that the functional test for all areas has been completed, the functional test is terminated.

  Here, when the test method shown in FIG. 31 is compared with the test method shown in FIG. 30, there is an advantage that the replacement frequency of the test socket is extremely low. There is a disadvantage that it is not possible to confirm non-defective products in consideration of the entire test area of the semiconductor device until the functional test of the test target area is performed. Therefore, when the socket replacement can be automated, it is desirable to carry out the test method shown in FIG.

  However, in any of the test methods shown in FIG. 30 or FIG. 31, compared with the conventional test method shown in FIG. 2, that is, a method of performing a functional test using a plurality of test boards by a plurality of test programs. By using the socket shown in FIG. 25 or FIG. 26, the function test of the multi-pinned semiconductor device exceeding the number of terminals provided on the test board with a single test board and a single test program. Can be performed. In particular, if the socket is automatically replaced in the same manner as the replacement of the semiconductor device, the non-defective product determination can be made dramatically in consideration of all the test areas by the test method shown in FIG. Therefore, it is possible to improve feedback to failure analysis and the like.

  In the above description, the PGA (Pin Grid Array Package) type and BGA (Ball Grid Array Package) type packages have been described, but it goes without saying that the present invention can be applied to other types of packages. Yes.

It is a block diagram of the conventional semiconductor device. It is a flowchart of the conventional test method. It is a perspective view explaining the conventional test method. It is a figure which shows arrangement | positioning of the signal terminal in the mounting surface of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the function test circuit with which the semiconductor device which concerns on Embodiment 1 of this invention was equipped. It is the figure which showed more specifically the circuit for setting the arbitrary area | regions on a mounting surface to a test state, and performing a functional test. 4 is a flowchart showing a test method for a semiconductor device according to the first embodiment of the present invention. It is the perspective view which looked at the test board with which IC was mounted from the back side. It is a figure which shows arrangement | positioning of the signal terminal in the mounting surface of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 10 is a diagram showing a configuration of a test board on which the semiconductor device shown in FIG. 9 is mounted. It is a figure which shows arrangement | positioning of the signal terminal in the mounting surface of the semiconductor device which concerns on Embodiment 3 of this invention. It is a figure which shows the structure of a region identification signal generation circuit. It is a figure which shows the structure of the test board carrying the semiconductor device shown by FIG. It is a figure which shows the terminal arrangement | positioning on the mounting surface of the semiconductor device which concerns on Embodiment 4 of this invention. FIG. 15 is a diagram showing a configuration of a test board on which the semiconductor device shown in FIG. 14 is mounted. It is a figure which shows the other example of arrangement | positioning of the terminal for identifying the area | region made into a test object. It is a figure which shows the structure of the frequency dividing circuit for producing | generating the signal supplied to an index terminal. It is a figure which shows the structure of the semiconductor device based on Embodiment 5 of this invention packaged. It is a figure which shows the structure of the test board with which the package shown by FIG. 18 was mounted. It is sectional drawing which shows the structure of the cross section in Y1-Y2 of the switch shown by FIG. It is sectional drawing which shows the structure of the cross section in X1-X2 of the switch shown by FIG. It is a figure which shows the terminal arrangement | positioning on the mounting surface of the semiconductor device which concerns on Embodiment 6 of this invention. It is a figure which shows the structure of the socket for the conventional A area | region test in which the semiconductor device shown by FIG. 22 was mounted. It is a figure which shows the structure of the conventional socket for B area | region tests in which the semiconductor device shown by FIG. 22 was mounted. It is a figure which shows the structure of the socket for A area | region tests which concerns on Embodiment 6 of this invention. It is a figure which shows the structure of the socket for B area | region tests which concerns on Embodiment 6 of this invention. It is a figure which shows the structure at the time of mounting the conventional A area | region test socket shown in FIG. 23 on the test board. It is a figure which shows the structure at the time of mounting the conventional B area | region test socket shown in FIG. 24 on the test board. FIG. 27 is a diagram showing a configuration when the A-area test socket shown in FIG. 25 or the B-area test socket shown in FIG. 26 is mounted on a test board. It is a flowchart which shows the 1st test method which concerns on Embodiment 6 of this invention. It is a flowchart which shows the 2nd test method which concerns on Embodiment 6 of this invention.

Explanation of symbols

1 Semiconductor device (IC)
1a Mounting surface 2, 2a, 2b Test board 9a Test control terminal 10a, 10b TAP terminal 11a, 11b Power supply terminal (VDD)
12a, 12b Power supply terminal (GND)
13a, 13b Signal input terminal 14a, 14b Signal output terminal 15 Outline center point 16 Test terminal 17, 17b, 34, 65b, 65c Wiring 18b Connect terminal 19b, 64b, 64c Terminal 20a TAP controller 20b Test control circuit 21a, 21b Flip-flop Circuits 22a and 22b Input / output terminal 23 Scan circuit 24 Frequency dividing circuit 30 Solder ball 31 Power supply terminal 32 Input / output signal terminal 33 Test signal supply terminal 63b and 63c Socket side terminal 66b Dummy terminal BRa and BRb Boundary scan registers TG1 and TG2 Transfer Gate

Claims (3)

A mounting surface comprising a plurality of regions, a test apparatus for testing a semiconductor device and a package having a asymmetric shape,
A test board for mounting the semiconductor device;
A plurality of button switches formed on the test board,
One of the plurality of button switches is disposed at a position to be pressed when the semiconductor device is placed on the test board, and is a test target in the plurality of regions based on the pressing by the semiconductor device. A test apparatus for outputting a signal for specifying a region . The test apparatus according to claim 1,
A test apparatus comprising: a connect terminal for supplying an external input signal to the area to be tested based on a signal from the button switch. The test apparatus according to claim 1,
2. A test apparatus according to claim 1, wherein a button switch pressed by the semiconductor device is different depending on an orientation of the semiconductor device placed on the test board.

Images