JP4022698B2 - Inspection circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inspection circuit board, and more particularly to an inspection circuit board that inputs and outputs test data so as to sequentially scan external input / output terminals of an integrated circuit.
[0002]
[Prior art]
An electronic circuit device including an integrated circuit (IC) is provided with a boundary scan test function in order to inspect the integrated circuit itself, inspect the connection between the integrated circuit and external logic, and the like. The boundary scan test is for inputting / outputting test data so as to sequentially scan all external input / output terminals of an integrated circuit such as an LSI or an ASIC.
[0003]
Therefore, in order to be able to perform a test by such a method, it is necessary that a required device on the circuit board supports this test method. If such a boundary scan test function is employed, several dedicated lines including control lines are required. Such a test makes it possible to verify the connection between the IC and the external logic in addition to the verification of the IC device itself as described above.
[0004]
A boundary scan compatible device having a boundary scan test function incorporates a test logic constituted by a TAP (test access port) controller in addition to an internal logic for performing an original function of the device. Then, by controlling this control line from an external host computer, a boundary scan test is performed.
[0005]
FIG. 8 shows a configuration in which ICs 2 and 3 composed of devices corresponding to boundary scan are mounted on the circuit board 1. Each of these ICs 2 and 3 is provided with a TAP controller 5 in addition to the internal logic 4 for performing the corresponding function. Therefore, a boundary scan test is performed by controlling the control line from the external host computer 7, thereby inspecting the ICs 2 and 3 and the connection between these ICs 2 and 3 and external logic. Will be performed.
[0006]
[Problems to be solved by the invention]
Many of the newly developed IC devices recently have a built-in TAP controller and many have a boundary scan test function. However, some existing IC devices do not have such a function. For such an IC device, a method of emulating a boundary scan test function by installing a test land in contact with a test pin on a circuit board is employed. However, as the number of IC pins increases, the sum of the areas of lands connected to the test pins on the circuit board increases accordingly, and there is a problem that high-density mounting is hindered by such lands.
[0007]
There is a method of adding a boundary scan test function using an inspection IC 6 instead of providing test pin lands on a circuit board. This method is illustrated in FIG. That is, for the IC 2 having only the internal logic 2 and not having the boundary scan test function, the inspection IC 6 is mounted on the circuit board 1 so as to correspond to the IC 2.
[0008]
By mounting such an IC 6, it becomes possible to add a boundary scan function to the IC 2, and it is possible to automatically perform an inspection of the IC 2 and a connection inspection between the IC 2 and external logic. . The inspection method in this case is a test using a control line using the host computer 7, and is the same as that in the configuration shown in FIG.
[0009]
According to the configuration shown in FIG. 9, it is possible to add a function for automatically performing a boundary scan test without providing a land on the circuit board 1 in contact with the test pin. However, in such a configuration, a pair of inspection ICs 6 must be added so as to correspond to the IC 2 having only the internal logic 4 on the circuit board 1, and such an IC 6 requires a large space, High-density mounting is hindered. Further, since the number of ICs increases, there is a disadvantage that the cost of the electronic circuit increases.
[0010]
The present invention has been made in view of such problems, and it is possible to add an inspection function to an integrated circuit having no inspection function without requiring a space larger than the size of the package. An object of the present invention is to provide an inspection circuit board .
[0011]
[Means for Solving the Problems]
The present invention provides an inspection circuit board that constitutes an inspection circuit that inputs and outputs test data so as to sequentially scan external input / output terminals of an integrated circuit.
Respectively Li Kui from bare chip for the integrated circuit does not have its own inspection function without so as to add a test cell Ru comprises a TAP controller,
An auxiliary intermediate substrate having a size substantially the same as the package of the integrated circuit is provided, the integrated circuit is mounted on the circuit substrate through the auxiliary intermediate substrate, and the inspection cell is mounted on the auxiliary intermediate substrate, The electrodes of the inspection cell are connected to the wiring pattern of the auxiliary intermediate substrate via solder balls, and the inspection cell is connected to the integrated circuit having no inspection function via the wiring pattern of the auxiliary intermediate substrate. The present invention relates to an inspection circuit board .
[0012]
External inspection by performing input and output of test data so as to sequentially scan all the external input and output terminals of the integrated circuit does not have the check function through the test cell from the host computer good I line Do. The inspection cell may be mounted on the auxiliary intermediate substrate so that the inspection cell is positioned between the integrated circuit and the auxiliary intermediate substrate. The inspection cell may be mounted on the auxiliary intermediate substrate so that the inspection cell is positioned between the integrated circuit and the circuit board. The inspection cells may be mounted on the auxiliary intermediate substrate so as to be arranged beside the integrated circuit.
[0014]
According to a preferred aspect of the present invention, for an integrated circuit consisting of an IC without a boundary scan circuit, an analog element and / or a digital element on the circuit board without increasing the size of the circuit board and the size of the IC. An integrated circuit that does not support the boundary scan test, for example, an IC dedicated to the boundary scan test function is additionally arranged outside the LSI in the same package size. The circuit board is inspected using the added IC. In particular, in this embodiment, the size of the circuit board can be reduced by re-creating a package having the same size as the target IC to which the boundary scan test function is added without directly placing the IC to be additionally arranged on the circuit board. It is characterized by not increasing it.
[0015]
In particular, an existing IC device such as an existing ASIC, LSI, logic, analog IC, or other active component, passive component, power supply component is added with a boundary scan test function, and the device and component size at that time are the original devices. And packaging technology that can be made the same as the component size. Therefore, the size of the circuit board does not increase, and for this reason, it is not necessary to change the design of the casing of a device on which such a circuit board is mounted. In addition, by applying such a circuit and combining with an IC having a boundary scan test function from the beginning, it is possible to inspect almost 100% of the circuit board alone and at a high speed.
[0016]
In another preferred embodiment of the present invention, an existing IC device is used as it is without being changed, and the number of pins of the IC device and the number of control pins to be added on the same size package as the IC device. A number of boundary scan cells equivalent to the sum of the above are installed. Here, in order to add a boundary scan test function, several wires are added on the circuit board as needed.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an electronic circuit having a boundary scan test function according to an embodiment of the present invention. The electronic circuit is mounted on the circuit board 11. That is, an IC 12 having a boundary scan function is mounted on the circuit board 11 and an auxiliary intermediate board 13 made of an interposer board is mounted. An IC 14 having no boundary scan test function is mounted on the auxiliary intermediate substrate. Boundary scan cells 15 and 16 for adding a boundary scan test function to the IC 14 are mounted together with the IC 14 on the auxiliary intermediate substrate 13 so that they are connected to each other by a predetermined wiring. It has become. Each of the boundary scan cells 15 and 16 includes a TAP controller 17.
[0018]
FIG. 2 shows the mounting state of the IC 14 and the boundary scan cells 15 and 16 on the circuit board 11. That is, the IC 14 and the boundary scan cells 15 and 16 are mounted on the circuit board 11 via the auxiliary intermediate board 13, respectively.
[0019]
Here, the lead 23 of the IC 14 is soldered to the wiring pattern 24 of the interposer substrate 13, and the wiring pattern 25 formed on the lower surface of the auxiliary intermediate substrate 13 is connected to the wiring pattern 27 on the circuit substrate 11 via the solder balls 26. To be connected to. On the other hand, the boundary scan cells 15 and 16 are connected to the wiring pattern 30 on the upper surface of the interposer substrate 13 via the solder balls 29. That is, here, the boundary scan cells 15 and 16 are positioned between the IC 14 and the interposer substrate 13. For example, as shown in FIG. 7, the IC 12 having the boundary scan test function has its lead 23 directly connected to the wiring pattern 24 on the circuit board 11 by soldering.
[0020]
As described above, in this embodiment, the IC 12 having the boundary scan test function is mounted in the same package as it is in the past. The package is used as it is for the IC 14 that does not have the boundary scan function. For the boundary scan cells 15 and 16, bare chips having no package are used. For the IC 14 and the boundary scan cells 15 and 16 that do not have the boundary scan function, an interposer substrate 13 such as CSP or BGA is used, and the boundary scan cells 15 and 16 are mounted on the upper surface of the interposer substrate 13. Thus, even when the boundary scan cells 15 and 16 are added, the space on the circuit board 11 uses only the same space as the size of the original IC 14. Here, the boundary scan cells 15 and 16 are arranged between the IC 14 and the interposer substrate 13.
[0021]
When the electronic circuit having the configuration shown in FIG. 1 is inspected, test data is sequentially scanned from the external host computer 18 using the boundary scan cells 15 and 16 to all the external input / output terminals of the IC 14. I / O is performed. Such a test makes it possible to perform an inspection of the IC 14 itself, a connection test between the IC 14 and external logic, and the like. That is, the boundary scan test is performed by controlling the control line from the external host computer 18.
[0022]
In general, when the circuit on the circuit board 11 cannot be inspected 100%, it is necessary to set a manual inspection process, which greatly increases the inspection time for one circuit board. In addition, when a manual inspection process is inserted, it is not always possible to reliably detect a defect, and there is a problem that it takes much time to investigate the cause of the defect.
[0023]
Conventionally, an in-circuit test is performed in order to inspect a connection portion of a device on a circuit board, or a non-contact electrical measuring device is used together. According to such a conventional inspection method, it is necessary to add test lands for performing each test on the circuit board, and a dedicated jig is required. For this reason, there is a problem that the cost and measurement time are increased.
[0024]
In addition, the size of the test land formed on the circuit board cannot be reduced too much because of the relationship with the diameter of the tip of the probe, which prevents the circuit board from being reduced in size. On the other hand, in order to manufacture a compact device, it is required to reduce the size of the circuit board and to reduce the cost by shortening the inspection time of the circuit board. In particular, by enabling 100% inspection of the circuit board, It is required to improve reliability.
[0025]
In the embodiment described above, the above three factors can be reduced by adding the boundary scan cells 15 and 16 made of bare chip ICs to the IC device 14 having no boundary scan test function without increasing the size of the device. It is possible to provide a small and highly reliable electronic circuit by solving this problem. Further, even if the boundary scan cells 15 and 16 are added, the circuit board 11 does not increase in size because only the same space as the package of the original IC device 14 takes up an area on the circuit board 11. There is no need to change the dimensions of the casing of the electronic device that houses the circuit board 11.
[0026]
Next, another embodiment will be described with reference to FIG. In this embodiment, boundary scan cells 15 and 16 for adding a boundary scan test function to the IC device 14 are arranged not on the upper surface of the interposer substrate 13 but on the lower surface. That is, the boundary scan cells 15 and 16 are mounted on the lower surface of the auxiliary intermediate substrate 13 made of an interposer substrate. For this reason, the boundary scan cells 15 and 16 are located between the auxiliary intermediate substrate 13 and the circuit board 11. become. Even with such a configuration, the circuit configuration is the same as in FIG. 1, and the same boundary scan test function as in FIG. 1 is added.
[0027]
FIG. 4 shows still another embodiment. In this embodiment, boundary scan cells 15 and 16 for adding a boundary scan test function are mounted on the upper surface of the auxiliary intermediate board 13 so as not to cross the leads 23 on the side of the circuit board 11. It is. Even in such a configuration, the circuit is the same as in FIG. 1, and the same functions as those in the first embodiment can be exhibited.
[0028]
FIG. 5 shows still another embodiment. In this embodiment, the IC 14 mounted on the auxiliary intermediate substrate 13 is such that the boundary scan cells 15 and 16 made of bare chips are mounted on the upper surface of the package of the IC 14 that does not have the boundary scan function. is there. Therefore, in this case, it is not necessary to mount the boundary scan cells 15 and 16 on the auxiliary intermediate substrate 13, and it is mounted later on the package of the bare chip ICs 15 and 16 and the IC device 14 for adding the boundary scan test function. That's fine.
[0029]
FIG. 6 shows still another embodiment. In this embodiment, the auxiliary intermediate substrate 13 made of an interposer substrate is omitted. That is, the IC 14 is directly mounted on the circuit board 11 like the IC 12, and the lead 23 is directly soldered to the wiring pattern 24 on the circuit board 11. The boundary scan cells 15 and 16 are mounted on the IC 14 package. Here, the electrodes of the boundary scan cells 15 and 16 are connected to the wiring pattern 30 on the package of the IC 14 via the solder balls 29. Therefore, even in such a configuration, the boundary scan test function is added to the IC 14 by the bare chips 15 and 16, and the circuit board 11 can be inspected 100% by the host computer 18.
[0030]
【The invention's effect】
The present invention as described above, in the inspection circuit substrate constituting the test circuit for performing input and output of test data so as to sequentially scan the external input and output terminals of the integrated circuit, against the inspection for no integrated circuit itself None to add a test cell that Ru comprising a forming Li Kui each TAP controller from the bare chip Te, comprising an auxiliary intermediate substrate of approximately the same size as the integrated circuit package, circuits integrated circuits via the auxiliary intermediate substrate Mounting on the substrate and mounting the inspection cell on the auxiliary intermediate substrate, the electrode of the inspection cell is connected to the wiring pattern of the auxiliary intermediate substrate via the solder ball, and inspection is performed via the wiring pattern of the auxiliary intermediate substrate The cell is connected to an integrated circuit having no inspection function .
[0031]
Therefore, according to the present invention, it is possible to perform the inspection by inputting / outputting test data so as to sequentially scan the external input / output terminals of the integrated circuit by adding the inspection cell composed of the bare chip. In addition, since only the inspection cell made of the bare chip is added, the space is hardly increased.
[0032]
According to the configuration in which test data is input / output so as to sequentially scan all external input / output terminals of an integrated circuit having no test function from an external host computer via test cells. The inspection function is added by the inspection cell on the auxiliary intermediate substrate, and the space on the circuit board is not increased.
[0033]
According to the configuration in which the inspection cell is mounted on the auxiliary intermediate substrate so that the inspection cell is located between the integrated circuit and the auxiliary intermediate substrate, an inspection function is added by the inspection cell.
[0034]
According to the configuration in which the inspection cell is mounted on the auxiliary intermediate substrate so that the inspection cell is located between the integrated circuit and the circuit board, an inspection function is added by the inspection cell.
[0035]
According to the configuration in which the inspection cells are mounted on the auxiliary intermediate substrate so as to be arranged beside the integrated circuit, an inspection function is added by the inspection cells.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration of an inspection circuit.
FIG. 2 is a longitudinal sectional view showing a mount of an IC and a boundary scan cell.
FIG. 3 is a vertical cross-sectional view of another embodiment showing a mount for an IC and a boundary scan cell.
FIG. 4 is a longitudinal sectional view of still another embodiment showing the mount of the IC and the boundary scan cell.
FIG. 5 is a longitudinal sectional view of still another embodiment showing the mount of the IC and the boundary scan cell.
FIG. 6 is a longitudinal sectional view of still another embodiment showing the mount of the IC and the boundary scan cell.
FIG. 7 is a longitudinal sectional view showing a mount of an IC having a boundary scan test function.
FIG. 8 is a block diagram of a circuit board on which an IC having a boundary scan function is mounted.
FIG. 9 is a block diagram of a circuit board on which an IC having a boundary scan function and an IC not having a boundary scan function are mounted.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Circuit board, 2, 3 ... IC, 4 ... Internal logic, 5 ... TAP controller, 6 ... Inspection IC, 7 ... Host computer, 11 ... Circuit board, 12 ... IC, 13 Auxiliary intermediate board (interposer board), 14 IC, 15, 16 ... Boundary cancel, 17 ... TAP controller, 18 ... Host computer, 23 ... Lead, 24, 25 ... Wiring pattern, 26 ... solder balls, 27 ... wiring patterns, 29 ... solder balls, 30 ... wiring patterns

Claims (5)

In an inspection circuit board constituting an inspection circuit for inputting / outputting test data so as to sequentially scan external input / output terminals of an integrated circuit,
A test cell consisting of a bare chip and each having a TAP controller is added to an integrated circuit that does not have a test function itself,
An auxiliary intermediate substrate having a size substantially the same as the package of the integrated circuit is provided, the integrated circuit is mounted on the circuit substrate through the auxiliary intermediate substrate, and the inspection cell is mounted on the auxiliary intermediate substrate, The electrodes of the inspection cell are connected to the wiring pattern of the auxiliary intermediate substrate via solder balls, and the inspection cell is connected to the integrated circuit having no inspection function via the wiring pattern of the auxiliary intermediate substrate. An inspection circuit board characterized by that.   Test is performed by inputting / outputting test data from an external host computer through the test cell so as to sequentially scan all external input / output terminals of the integrated circuit not having the test function. The inspection circuit board according to claim 1.   The inspection circuit board according to claim 2, wherein the inspection cell is mounted on the auxiliary intermediate substrate so that the inspection cell is positioned between the integrated circuit and the auxiliary intermediate substrate.   The inspection circuit board according to claim 2, wherein the inspection cell is mounted on the auxiliary intermediate substrate so that the inspection cell is located between the integrated circuit and the circuit board.   3. The inspection circuit board according to claim 2, wherein the inspection cells are mounted on the auxiliary intermediate substrate so as to be arranged beside the integrated circuit.

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