JP5144170B2 - Mounting method of semiconductor device - Google Patents

Description

  The present invention provides an arrangement of external terminals in a semiconductor device having a surface-mount package form represented by SiP (system in package), BGA (ball grid array), LGA (land grid array), WPP (wafer package process) and the like. Concerning structure.

  As semiconductor devices are highly integrated and highly functional, many functions tend to be built in one semiconductor device. As a result, the number of terminals increases, and if the terminal arrangement is performed while simply ensuring the terminal pitch, the package becomes larger. Thus, there has been a demand for cost reduction or package size reduction.

  In Patent Document 1 found in the prior art search after the completion of the present invention, terminals that are not used by the customer (usually test terminals that do not need to be connected to the substrate) and terminals that are used by the customer are divided into areas. As compared with the above, a technique for narrowing the former terminal arrangement is described. Patent Document 2 describes a technique for arranging inspection terminals (inspection terminals used only at the time of inspection) with LGA (not forming bumps) between external terminals for BGA operation arranged in a lattice shape.

JP 2004-342947 A JP 2004-22664 A

  The present inventor has examined the arrangement of many external terminals in a limited space of a semiconductor device. For example, in a general-purpose microcomputer equipped with a central processing unit and a large number of peripheral circuits, when the functions used for each customer are different, external terminals that are not used depending on the customer are generated. At this time, if an unused terminal is not provided as an external terminal, the arrangement of the external terminals can be increased accordingly. However, since the semiconductor manufacturer must perform a device test before shipping, if the function of the external terminal is different for each customer, even if it is a semiconductor device having the same circuit configuration, the test The restrictions on the items are different, leading to increased cost of development mass production, such as new test program development and increased test time. Therefore, we examined the arrangement of both external terminals that customers use and external terminals that are not used, and making the latter terminal arrangement pitch smaller than the former. However, it has been found by the present inventor that it is inconvenient to simply determine the size of the terminal arrangement pitch by such cutting. First, in order to prevent undesired leakage on the mounting board when the height of the terminal with a small terminal arrangement pitch not used by the customer is the same as the terminal with the large terminal arrangement pitch used by the customer, the customer There is a restriction that it is better not to form a wiring pattern directly under the unused terminal. This point is not considered in Patent Document 1. Second, in order to perform a failure analysis of a semiconductor device that has been returned to a semiconductor manufacturer due to a failure if terminals that are not used by the customer are formed only by lands in order to reduce the height and bumps are not provided. It takes time and effort to expose the land constituting the terminal not used by the customer from the underfill resin. Patent Document 2 does not consider this point. Third, even external terminals that are not used by customers may be used for screening. When the arrangement pitch of such external terminals is small, the tester terminals of the screening tester must correspond to them, and the tester Incurs an increase in costs. This point is not considered in Patent Documents 1 and 2. The screening test is an operation that gives an operation voltage and operation timing higher than normal operation, and it is not necessary to verify all the circuit functions like the device function test. May be. By using the output function for the circuit connected to the output terminal or input / output terminal, it is possible to transmit the timing and voltage signals suitable for the acceleration test to the external interface buffer via the internal circuit operation. It is. Therefore, the external terminals used for screening can be selected. In this sense, since there is a possibility that the number of terminals can be limited for the external terminals used in the screening test, there remains room for reducing the pitch as in the case of other test terminals. Revealed by.

  An object of the present invention is to provide a semiconductor device that can alleviate restrictions on the mounting substrate side for suppressing undesired leakage with an external terminal.

  Another object of the present invention is to provide a semiconductor device in which external terminals can be easily exposed from an underfill resin for failure analysis or the like.

  Still another object of the present invention is to provide a semiconductor device capable of suppressing an increase in cost of a screening test.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the external terminal of the semiconductor device is divided into a bump having a relatively large diameter and pitch and a small bump, and the latter is arranged closer to the center of the semiconductor device than the former. A part of the large bump is used for connection to a mounting substrate on which the semiconductor device is mounted, and the remainder of the large bump is not used for connection to the mounting substrate, but is used for connection to a screening tester. The small bumps are not used for connection with a mounting substrate on which a semiconductor device is mounted, nor for connection with a screening tester. As a result, there is no risk of unwanted leakage even if there is a wiring pattern directly under the small bump area on the mounting substrate side. Even if small bumps are covered with underfill resin, they can be easily exposed by scraping the surface, making it easier to expose terminals for failure analysis than when only lands are provided instead of small bumps. become. Since the pitch and diameter of the external terminals connected to the screening tester are both increased, a special pin pitch conversion adapter or the like is not required for the screening test, and the positioning of the semiconductor device as the DUT with respect to the probe does not particularly require high accuracy. .

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to relax the restrictions on the mounting substrate side for suppressing undesired leaks with the external terminals.

  Further, it is easy to expose the external terminal from the underfill resin for failure analysis or the like.

  Moreover, the cost increase of a tester can be suppressed.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (1) according to a typical embodiment of the present invention includes a semiconductor integrated circuit chip (2) on which a circuit is formed. The semiconductor device includes a plurality of first external terminals (Pus, Pu, Ps) arranged at a predetermined pitch, and a minimum pitch closer to the center of the semiconductor device than the first external terminal is smaller than the predetermined pitch. And a plurality of second external terminals (P). The first external terminal is formed by a first bump (BMP1) connected to a first land (LND1). The second external terminal is connected to a second land (LND2) smaller than the first land and is formed by a second bump (BMP2) having a height and diameter smaller than those of the first bump. As a result, there is no possibility of undesired leakage even if there is a wiring pattern immediately below the second bump region on the mounting substrate side. Even if the second bump is covered with an underfill resin, it can be easily exposed by scraping the surface. Compared with the case where only the land is provided instead of the second bump, the terminal exposure work for failure analysis Becomes easier.

  As one specific form, the plurality of first external terminals are used for connection to a mounting substrate on which a semiconductor device is mounted, Pu, connection to the mounting substrate, and connection to a screening tester. It is assigned to a terminal (Pus) and a terminal (Ps) that is not used for connection to the mounting board and is used for connection to a screening tester. The plurality of second external terminals are assigned to terminals (P) that are not used for connection to the mounting substrate and are not used for connection to the screening tester. With such terminal assignment, there is no risk of unwanted leakage even if there is a wiring pattern immediately below the second bump area on the mounting board side. Even if the second bump is covered with an underfill resin, it can be easily exposed by scraping the surface. Compared with the case where only the land is provided instead of the second bump, the terminal exposure work for failure analysis Becomes easier. Regardless of whether or not it can be connected to the mounting board, the external terminals connected to the screening tester are formed by the first bumps having a large pitch and diameter, so that a special pin pitch conversion adapter is not required for the tester. The positioning of the semiconductor device as a DUT with respect to the above does not require high accuracy.

  [2] A semiconductor device according to another embodiment is different from the semiconductor device described above in that the second external terminal is formed by a second land smaller than the first land. And terminal function assignment to the second external terminal are the same ((D) and (E) in FIG. 1). According to this, there is no need to form bumps to form the second external terminals, but it takes time to expose the second external terminals from the underfill resin for failure analysis. Other functions and effects are the same as described above.

  [3] A semiconductor device according to another embodiment is different from the semiconductor device in that the first external terminal is formed by the first land and the second external terminal is formed by the second land. The assignment of terminal functions to the first external terminal and the second external terminal is the same ((F) and (G) in FIG. 1). According to this, there is no need to form bumps, but since the probe is brought into direct contact with the land in a screening test or the like, if the contact pressure is too high or the probe positioning system with respect to the DUT is too low, the semiconductor chip May cause mechanical damage.

  [4] As a more specific form in each of the semiconductor devices, a terminal that is not used for connection to the screening tester among the plurality of first external terminals is an output terminal or an input / output terminal. By using the output function for the circuit connected to the output terminal or input / output terminal, it is possible to transmit the timing and voltage signals suitable for the acceleration test to the external interface buffer via the internal circuit operation. It is. Therefore, it can contribute to the reduction of the number of terminals used only for screening.

  Of the plurality of first external terminals, a terminal used for connection to the screening tester is an input terminal. As is clear from the above, it is preferable that at least the input terminal is a screening terminal.

  As a more specific form, the circuit includes a first circuit and a second circuit connected to the first circuit by a signal line. Part or all of the external terminals connected to the second circuit are the second external terminals, and all of the external terminals connected to the first circuit are the first external terminals. Even if a circuit that is not used is included in a part of the second circuit, the circuit becomes a test target. This is because, since the second circuit is connected to the first circuit by a signal line, a failure of the unused circuit causes a malfunction of other circuits. This is the significance of connecting the second external terminal to a circuit that is not used. Even if the second circuit is not connected to the first circuit by a signal line, if the external power supply terminal is shared, the second external terminal can be Needless to say, it is meaningful to set up.

  As a more specific form, the first circuit includes a central processing unit that executes an instruction, and the second circuit includes a peripheral circuit controlled by the central processing unit. This is because a peripheral circuit used in a semiconductor device such as a microcomputer may be different for each customer.

  As another specific form, wiring having one or a plurality of the semiconductor integrated circuit chips, mounting the semiconductor integrated circuit chip on one surface, and forming the first external terminal and the second external terminal on the other surface A grid array package form having a substrate can be adopted for a semiconductor device. The grid array package form is a package form such as BGA or LGA.

  As another specific form, a lead-out wiring extending in connection with the bonding pad is formed on the bonding pad forming surface of the semiconductor integrated circuit chip, and the first external terminal and the second external terminal correspond to each other. A wafer process package form formed at the leading end of the lead wiring to be used may be adopted in the semiconductor device.

  [5] A semiconductor device according to another embodiment is a terminal that is not used for connection to the mounting substrate and is used for connection with the screening tester among the first external terminals in the semiconductor device of each of the above embodiments. Is changed to a terminal (PPs) having a smaller size and diameter so that only a pitch larger than that of the second external terminal is maintained.

  More specifically, the first external terminal is connected to a first bump (BMP_F) connected to the first land and a second land smaller than the first land, and has a smaller height and diameter than the first bump. The second bump (BMP_S) is formed. The second external terminal is formed by a third bump (BMP_T) connected to a third land smaller than the first land and having a height and diameter smaller than that of the first bump electrode. The plurality of first bumps are assigned to terminals used for connection to a mounting board on which a semiconductor device is mounted, and terminals used for connection to the mounting board and connection to a screening tester. The second bump is assigned to a terminal that is not used for connection to the mounting substrate and is used for connection to a screening tester. The plurality of third bumps are assigned to terminals that are not used for connection to the mounting substrate and are not used for connection to the screening tester.

  According to this, compared with the embodiment described above, the same operation and effect as described above are obtained except that it is necessary to increase the positioning accuracy of the semiconductor device as the DUT with respect to the probe in the screening test. .

  In contrast to this embodiment, the second external terminal is changed to a third land (LND_T) smaller than the first land (LNF_F), and all of the first external terminal and the second external terminal are landed. It is also possible to adopt the changes formed in

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 2 illustrates a block diagram of a semiconductor device according to the present invention. The semiconductor device 1 shown in the figure has a semiconductor integrated circuit chip 2 formed on one semiconductor chip such as single crystal silicon by, for example, a CMOS integrated circuit manufacturing technique. The semiconductor integrated circuit chip 2 includes first circuits (FCCT) 3 and 5 and a second circuit (SCCT) 4, which are connected by a bus 6. The first circuits 3 and 5 have, for example, a central processing unit (CPU) that fetches and executes instructions and a random access memory (RAM) used for a work area of the CPU. The second circuit 4 is a peripheral circuit of the CPU. For example, a timer (TMR), a serial communication interface (SCI), an ADC (analog / digital converter), a DAC (digital / analog converter), a watch dog timer. (WDT), digital signal processor (DSP), etc.

  The semiconductor integrated circuit chip 2 is sealed in a surface mount type package form such as BGA, LGA or WPP, and external terminals Pus, Pu, Ps and P, which are typically shown as external terminals, are arranged in the package. . Here, the case where the second circuit 4 is not used is taken as an example. The first circuits 3 and 5 are connected to a mounting substrate (not shown) on which the semiconductor device 1 is mounted, and the other second circuit 4 is used. No connection to the mounting board is required. The external terminal Pu is used for connection to a mounting board on which the semiconductor device 1 is mounted and is not used for connection with a screening tester. The terminal Pus is used for connection to the mounting board and for connection with a screening tester. It is. The terminal Ps is not used for connection to the mounting board and is used for connection to a screening tester, and the terminal P is not used for connection to the mounting board and is used for connection to a screening tester. There is no terminal. In short, the terminals Pus and Pu are terminals connected to the mounting board, and P and Ps are terminals not connected to the mounting board. The terminals Pus and Ps connected to the screening tester straddle both the terminals connected to the mounting substrate and the terminals not connected. The suffix “u” of the external terminals Pus, Pu, Ps means that they are connected to the mounting board, and the suffix “s” means that they are connected to the screening tester.

  FIG. 3 illustrates a state where the semiconductor device 1 is mounted on a mounting substrate. 7 is a mounting substrate, and 8 is a general term for wiring patterns to which the semiconductor device 1 is connected, and is connected to the terminals Pus and Pu.

  FIG. 4 illustrates a state in which a plurality of semiconductor devices 1 are connected to a screening tester (TEST) 9. The terminals Pus and Ps connected to the screening tester 9 are, for example, an input port terminal I_PORT, a clock input terminal EXTAL, a reset signal input terminal RES, a standby signal input terminal STBY, a mode signal input terminal MOD, data input terminals D0 to D1, and a power supply A terminal VCC and a ground terminal VSS are used. Of the terminals connected to the mounting substrate 7, the terminals Pu not connected to the screening tester are, for example, an input / output port terminal IO_PORT, an output port terminal O_PORT, and address output terminals A0 to A2. The external terminals P, Pus, Ps, and Pu in FIGS. 3 and 4 are shown along the edge of the semiconductor device 1 in the drawing, but in actuality, they are arranged in a package form of BGA, LGA, and WPP. Yes. Also, the number of terminals is different in drawing, but is actually matched.

  FIG. 1 illustrates an arrangement of external terminals of a semiconductor device according to the present invention. 1A is a plan view, and FIGS. 1B to 1G are front views. As illustrated in FIG. 1A, in the semiconductor device 1, the terminals Pus, Pu, and Ps constitute first external terminals arranged at a predetermined pitch, for example, 1 mm pitch in the xy direction. The terminal P constitutes a second external terminal disposed at a position closer to the center of the semiconductor device 1 than the first external terminals Pus, Pu, Ps at a pitch smaller than the 1 mm pitch. The first external terminals Pus, Pu, Ps are formed by first bumps BMP1 connected to the first lands LND1 as illustrated in FIG. The second external terminal P is connected to a second land LND2 smaller than the first land LND1, and is formed by a second bump BMP2 having a height and diameter smaller than those of the first bump BMP1. In FIG. 1B, illustration of the lands LND1 and LND2 is omitted. FIG. 1B schematically shows a side cross section of a BGA package form in which all of the first external terminals Pus, Pu, Ps and the second external terminal P are formed by bumps. It is also possible to adopt a structure in which lands are formed thick as in (C) (BGA_P package form), and a structure in which second external terminals P are formed in lands as in (D) (BGA / LGA package form). . Further, a structure in which the land is formed thick in the form (D) as shown in FIG. 1E (BGA_P / LGA_P package form), and the first external terminals Pus, Pu, Ps and the second external terminals as shown in FIG. It is also possible to adopt a structure in which both the terminals P are formed by lands (LGA package form) or a structure in which the lands are formed thickly in the form (F) as in (G) (LGA_P package form).

  FIG. 6 shows a comparative example in which all of the first external terminals Pus, Pu, Ps and the second external terminal P are formed with the same pitch and the same size with respect to the external terminal structure of FIG. 6A is a plan view, and FIGS. 6B to 6G are front views. . 6A to 6G correspond to FIGS. 1A to 1G.

  According to the semiconductor device 1, the following operational effects are obtained.

  [1] In the BGA form of FIG. 1B, the BGA_P form of (C), the BGA / LGA form of (D), and the BGA_p / LGA_P form of (E), the second external terminal P is the first external terminal Pus, Since the height and diameter are smaller than those of Ps and Pu, even if there is a wiring pattern immediately below the region of the second external terminal P on the mounting substrate 7, there is no possibility of unwanted leakage.

  [2] In the BGA form of FIG. 1B and the BGA_P form of FIG. 1C, even if the second electrode P is covered with the underfill resin, it can be easily exposed by scraping the surface. As compared with the case where the second electrode P is formed only by the land instead of the bump as in the LGA form of FIG. In short, it is possible to increase the cutting allowance for the underfill resin covering the second electrode, and to avoid the possibility of damaging the circuit area of the semiconductor integrated circuit chip.

  [3] The external terminals Ps and Pus connected to the screening tester 9 regardless of whether or not they can be connected to the mounting board 7 are pitches in the form of (B), (C), (D), and (E) in FIG. The screening tester 9 does not require a special pin pitch conversion adapter or the like, and positioning of the semiconductor device 1 as a DUT with respect to the probe does not require particularly high accuracy. As a result, the test cost of the screening test can be reduced. In the form of (F) and (G) in FIG. 1, the second external terminals P are arranged at the same large pitch as described above, but are formed by lands or posts with thickened lands. The positioning of the semiconductor device 1 requires higher accuracy than the forms (B), (C), (D), and (E). This is because mechanical damage to the circuit area of the semiconductor integrated circuit chip by the probe must be reduced. As described above, the screening tester does not require a special pin pitch conversion adapter.

  [4] Of the plurality of first external terminals Pus, Ps, Pu, a terminal Pu that is not used for connection to the screening tester is an output terminal or an input / output terminal, and is a circuit connected to the output terminal or the input / output terminal. On the other hand, by using the output function, it is possible to transmit a timing or voltage signal suitable for the acceleration test to the external interface buffer through the internal circuit operation. Therefore, it is possible to reduce the number of terminals used only for screening, and thus it is possible to suppress an excessive increase in the number of large external terminals that should be arranged with a large pitch.

  [5] Even when a part of the internal circuit of the semiconductor device 1 such as a general-purpose microcomputer includes a circuit that is not used by a specific customer, by reducing the circuit or disconnecting from the internal bus, the semiconductor device It is not necessary to change the mask pattern for manufacturing. At this time, devices that are not used by a specific customer are also subject to device testing. For example, the circuit 4 not used as shown in FIG. 2 may affect the first circuits 3 and 5 via the bus 6. Therefore, it is indispensable to arrange a terminal that is not used by a specific user, such as the external terminal P in FIG. 2, for at least a device test, but it contributes to miniaturization of the package by reducing the terminal pitch and the terminal size. To do.

  FIG. 7 shows another example of the semiconductor device. FIG. 7A is a plan view, and FIGS. 7B to 7D are front views. The semiconductor device 1A shown in the figure is different from the semiconductor device 1 described in FIG. 1 in that the external end terminals used for connection to the screening tester and not used for connection to the mounting substrate are formed as small as PPs. Is different. The external terminals PPs are also arranged at the same pitch as the other first external terminals Pus and Pu. That is, the external terminals Pus and Pu are formed by the first bumps BMP_F connected to the first lands, and the external terminals PPs are connected to the second lands smaller than the first lands and more than the first bumps. It is formed by the second bump BMP_S having a small height and diameter. The external terminal P is formed by a third bump BMP_T connected to a third land smaller than the first land and having a height and diameter smaller than those of the first bump electrode. Since other configurations are the same as those in FIG. 1, detailed description thereof is omitted. FIG. 7 illustrates, in addition to the plan view of (A), schematic side cross-sectional structures of (B) BGA form, (C) BGA / LGA form, and (D) LGA form. According to this, compared with the structure of FIG. 1 described above, the same operation and effect as described above except that it is necessary to increase the positioning accuracy of the semiconductor device as the DUT with respect to the probe in the screening test. obtain.

  FIG. 8 shows another example in which the number and arrangement of the first external terminals Pus, Pu, Ps and the second external terminals P are different. 8A is a plan view, and FIGS. 8B to 8D are front views. Compared to FIG. 1, the pitch of the first external terminals Pus, Pu, Ps is increased, and the arrangement form of the second external terminals P is different. In this arrangement, the same effect as in FIG. 1 is obtained.

  FIG. 9 illustrates a configuration in which external terminal terminals used only for connection with the screening tester are formed smaller by third bumps BMP_T, such as PPs, with respect to the terminal arrangement of FIG. 9A is a plan view, and FIGS. 9B to 9D are front views. The external terminals PPs are also arranged at the same pitch as the other first external terminals Pus and Ps. Even in this configuration, the same operations and effects as in FIG. 7 are obtained.

  FIG. 10 illustrates a terminal arrangement in the WPP package form. In the WPP package form, a lead-out wiring LIN extending to connect to the bonding pad PAD is formed on the bonding pad forming region PAD of the semiconductor integrated circuit chip, and the first external terminals Pus, Pu, Ps and the second external terminal P are formed. Are formed by, for example, solder bump electrodes at the tip of the corresponding lead-out wiring LIN. Also in the WPP package form, the same effect as in the case of FIG. 1 is obtained.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the shape of the bump is not limited to a spherical shape, and may be a cubic shape, an inverted triangular truncated cone shape, an inverted truncated truncated cone shape, or the like. The number of external terminals, the number of semiconductor integrated circuit chips contained in one package, the specific types and numbers of the first circuit and the second circuit, and the like can be changed as appropriate.

  In the embodiment of the present invention, the diameter of the first land arranged around the wiring substrate (arranged along each side) to which the first bump is connected is set to be the second value to which the second bump is connected. Although it has been described that it is smaller than the diameter of the land, the present invention is not limited to this. For example, as shown in FIG. 11, it is not connected to the electrode of the mounting substrate on which the semiconductor device is mounted. As long as the second land used for connection to the second land has a second bump lower than the height of the first bump, the second land has the same diameter as the first land. Good. This is because the screening test is performed by bringing the probe needle into contact with the bump, and at this time, the probe needle is surely brought into contact with the bump when the land diameter is relatively large. However, if the land is simply increased, the height of the bump formed is also increased. The bump used for the screening test is not connected to the electrode of the mounting substrate on which the semiconductor device is mounted. Therefore, the bump height should be as low as possible. Therefore, FIG. 11 (FIG. 11B is a cross-sectional view taken along the line AA ′ in FIG. 11A, FIG. 11C is a cross-sectional view taken along the line BB ′ in FIG. 11A, and FIG. If D) is configured as shown in the cross-sectional view taken along the line CC ′ in FIG. 11A, the screening test can be performed more reliably while avoiding contact with the mounting substrate.

Further, in the WPP package according to the embodiment of the present invention, the distance between adjacent bonding pads is extended from the bonding pad of the semiconductor chip (semiconductor integrated circuit chip) via the lead wiring, and a solder bump is formed at the leading end of the lead wiring. However, the present invention is not limited to this. For example, if a plurality of bonding pads formed on a semiconductor chip are spaced widely in advance, it is necessary to extend the lead-out wiring from each bonding pad. There is no. However, since the dimensions (area and diameter) of the bonding pads formed on the semiconductor chip are relatively small compared to the lands formed on the wiring substrate, the bonding pads are formed when the solder bumps are formed directly on these bonding pads. Solder bumps that are smaller are also smaller (lower). Therefore, as shown in FIG. 12, a lead-out wiring is formed on the bonding pad via the first insulating film and the second insulating film, and the area to which the solder bump is connected is widened so that the formed solder bump is relatively The mounting strength of the WPP package (semiconductor device, semiconductor chip, semiconductor integrated circuit chip) can be improved.
In the embodiment of the present invention, a BGA type or LGA type package is also described. However, a semiconductor chip (semiconductor integrated circuit chip) covered with a resin sealing body (sealing body) and a semiconductor chip are provided. As shown in FIG. 13, a plurality of wires may be used for electrical connection with the wiring board to be supported (mounted). Further, as shown in FIG. 14, flip-chip connection is performed via bump electrodes. Also good.

FIG. 1 is an explanatory view illustrating the arrangement of external terminals in a semiconductor device according to the present invention. FIG. 2 is a block diagram illustrating a semiconductor device according to the present invention. FIG. 3 is an explanatory view illustrating a state in which the semiconductor device is mounted on the mounting substrate. FIG. 4 is an explanatory view illustrating a state in which a plurality of semiconductor devices are connected to the screening tester. FIG. 5 is a longitudinal sectional view illustrating a first bump on which a first external terminal is formed and a second bump on which a second external terminal is formed. It is explanatory drawing which shows the comparative example at the time of forming all the 1st external terminals and 2nd external terminals with the same pitch and the same magnitude | size with respect to the external terminal structure of FIG. FIG. 7 is an explanatory view illustrating a semiconductor device that is different from the semiconductor device described in FIG. 1 in that an external terminal used for connection to a screening tester is not used for connection to a mounting substrate. is there. FIG. 8 is an explanatory view showing an example of another semiconductor device in which the pitch of the first external terminals is larger than that in FIG. 1 and the arrangement form of the second external terminals is different. FIG. 9 is an explanatory view illustrating a semiconductor device in which external terminal terminals used only for connection with a screening tester are formed smaller by third bumps BMP_T in the terminal arrangement of FIG. FIG. 10 is an explanatory view illustrating a terminal arrangement in a semiconductor device adopting the WPP package form. FIG. 11 is an explanatory view illustrating the arrangement of external terminals of a modification of the semiconductor device according to the present invention. FIG. 12 is an explanatory view illustrating a terminal arrangement of a modification of the semiconductor device adopting the WPP package form. FIG. 13 is an explanatory view showing an example in which a plurality of wires are used for electrical connection between a semiconductor chip covered with a resin sealing body and a wiring board supporting the semiconductor chip. FIG. 14 is an explanatory view showing an example in which a flip chip connection is made via a bump electrode to an electrical connection between a semiconductor chip covered with a resin sealing body and a wiring board supporting the semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor integrated circuit chip 3, 5 1st circuit (FCCT)
4 Second circuit (SCCT)
6 Bus Pu Terminal used for connection to mounting board and not used for connection to screening tester Pus Terminal used for connection to mounting board and connection to screening tester Ps Not used for connection to mounting board and Terminal P used for connection to screening tester P Terminal not used for connection to mounting board and not used for connection to screening tester 7 Mounting board 8 Wiring pattern 9 Screening tester (TEST)
LND1 First land BMP1 First bump LND2 Second land BMP2 Second bump BMP_F First bump BMP_S Second bump BMP_T Third bump PAD Bonding pad formation area LIN Lead wiring

Claims (5)

A semiconductor device mounting method including the following steps:
(A) a first surface, a plurality of first lands formed on the first surface and arranged at a first pitch, and formed on the first surface and from the plurality of first lands And a plurality of second lands disposed at a second pitch smaller than the first pitch closer to the center of the first surface than the plurality of first lands, and the plurality of first lands. A plurality of first bumps connected to the lands, having a first height and having a first diameter, and connected to the plurality of second lands, respectively, and being smaller than the first height Providing a semiconductor device including a plurality of second bumps having a second height and a second diameter smaller than the first diameter;
(B) mounting the semiconductor device on a mounting substrate via the plurality of first bumps, and covering the plurality of first bumps and the plurality of second bumps with an underfill resin ;
here,
The semiconductor device further includes a semiconductor integrated circuit chip on which a circuit is formed,
The circuit includes a first circuit and a second circuit connected to the first circuit by a signal line,
A part or all of the external terminals connected to the second circuit are the second bumps,
All of the external terminals connected to the first circuit are the first bumps. The method for mounting a semiconductor device according to claim 1,
The plurality of first bumps are not used for connection to the mounting substrate, a terminal used for connection to the mounting substrate and a connection to a screening tester, and a connection to the mounting substrate, and screening. Assigned to the terminal used to connect to the tester,
The plurality of second bumps are assigned to terminals that are not used for connection to the mounting substrate and are not used for connection to the screening tester. In the mounting method of the semiconductor device according to claim 2,
Of the plurality of second bumps, a terminal that is not used for connection with the screening tester is an output terminal or an input / output terminal. In the mounting method of the semiconductor device according to claim 3,
Of the plurality of first bumps, a terminal used for connection to the screening tester is an input terminal. The method for mounting a semiconductor device according to claim 1,
The first circuit includes a central processing unit that executes instructions;
The second circuit includes a peripheral circuit controlled by the central processing unit.

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