JPH01129432A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH01129432A JPH01129432A JP62289075A JP28907587A JPH01129432A JP H01129432 A JPH01129432 A JP H01129432A JP 62289075 A JP62289075 A JP 62289075A JP 28907587 A JP28907587 A JP 28907587A JP H01129432 A JPH01129432 A JP H01129432A
- Authority
- JP
- Japan
- Prior art keywords
- positioning
- probes
- terminals
- lsi
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 abstract description 32
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路に関するもので、特に集積回路をウェ
ハー段階でテストする際に用いる探針と、LSI端子と
の位置決め構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuits, and particularly to a structure for positioning a probe used when testing an integrated circuit at the wafer stage and an LSI terminal.
ウェハー段階で集積回路チップ(以下LSIという)の
電気的なテストを行う際には、いわゆるLSIテスター
が使われるのが普通である。LSIテスターでの電気テ
ストはLSIの信号端子及び電源端子にテスターの探針
からテストに応じた信号及び電源を供給することによっ
て行われる。When electrically testing integrated circuit chips (hereinafter referred to as LSI) at the wafer stage, a so-called LSI tester is usually used. An electrical test with an LSI tester is performed by supplying a signal and power according to the test to the signal terminal and power supply terminal of the LSI from the probe of the tester.
従来、この種のLSIをテストする際には、テストに先
立って探針とLSI端子中心との位置決めを、LSIの
全端子について目視で行う必要があった。Conventionally, when testing this type of LSI, it has been necessary to visually position the probe and the center of the LSI terminals for all terminals of the LSI prior to the test.
上述した従来のLSIは電気テスト時に探針とLSI端
子とを正確に位置決めするのに多大な労力を必要とする
欠点がある。The above-mentioned conventional LSI has the disadvantage that it requires a great deal of effort to accurately position the probe and the LSI terminal during electrical testing.
本発明の目的は前記問題点を解消した集積回路を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that eliminates the above-mentioned problems.
上述した従来のLSIに対し、本発明は集積回路の電気
テスト時における探針でのブロービングを行った際に、
探針間が完全に接続されているか否かを電気的に外部モ
ニタするという相違点を有する。In contrast to the above-mentioned conventional LSI, the present invention provides the following advantages when performing probing with a probe during electrical testing of integrated circuits.
The difference is that whether or not the probes are completely connected is externally monitored electrically.
本発明は一部が集積回路チップ内の配線パターンを介し
て互いに接続されている位置決め端子を通常の入出力端
子及び電源端子とは別個に有することを特徴とする集積
回路である。The present invention is an integrated circuit characterized in that it has positioning terminals, some of which are connected to each other via wiring patterns within the integrated circuit chip, separately from normal input/output terminals and power supply terminals.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の実施例を示す図である。図において、
10はLSIチップ、11は入出力信号及び電源を供給
する端子、12はLSIテスター等のテスト機器からテ
スト信号を端子11に供給する探針、13〜16はLS
Iチップ10の4コーナーに設けられた位置決め端子、
121〜124は前記位置決め端子13〜16に対応し
た位置決め探針、131〜132ば前記位置決め端子1
3と14及び15と16を接続するLSIチップ10内
の配線パターンをあられしている。LSIの電気テスト
の際には、位置決め探針121と124の間にオープン
モニター17を接続し、位置決め探針122と123は
外部配線18で接続しておく。FIG. 1 is a diagram showing an embodiment of the present invention. In the figure,
10 is an LSI chip, 11 is a terminal that supplies input/output signals and power, 12 is a probe that supplies test signals from test equipment such as an LSI tester to terminal 11, and 13 to 16 are LS
Positioning terminals provided at the four corners of the I-chip 10,
121 to 124 are positioning probes corresponding to the positioning terminals 13 to 16; 131 to 132 are the positioning terminals 1;
The wiring patterns within the LSI chip 10 connecting 3 and 14 and 15 and 16 are shown. When electrically testing an LSI, an open monitor 17 is connected between the positioning probes 121 and 124, and the positioning probes 122 and 123 are connected by an external wiring 18.
次に本発明の動作について説明する。Next, the operation of the present invention will be explained.
第1図は位置決め探針121〜124が位置決め端子1
3〜16の全てに正確に位置決めされている場合を示し
ている。この場合、位置決め探針121→LSI内の配
線パターン131→位置決め探針122→外部配線18
→位置決め探針123→LSI内の配線パターン132
→位置決め探針124という閉ループがオープンモニタ
ー17を介して構成される。In Fig. 1, the positioning probes 121 to 124 are connected to the positioning terminal 1.
3 to 16 are all accurately positioned. In this case, positioning probe 121 → wiring pattern 131 inside LSI → positioning probe 122 → external wiring 18
→Positioning probe 123→Wiring pattern 132 inside LSI
→A closed loop called the positioning probe 124 is configured via the open monitor 17.
オープンモニター17で位置決め探針121と124間
の抵抗値を測定することにすれば、第1図のように探針
の位置決めが正確に行われているときには低抵抗値を示
すことになる。If the open monitor 17 measures the resistance value between the positioning probes 121 and 124, it will show a low resistance value when the probes are accurately positioned as shown in FIG.
位置決め探針121〜124のうち1本以上が位置決め
端子13〜16から外れている場合、位置決め探針12
1〜124間の一部がオープン状態になり、オープンモ
ニター17での抵抗値は非常に大きい値あるいは無限大
を示すことになる。If one or more of the positioning probes 121 to 124 is detached from the positioning terminals 13 to 16, the positioning probe 12
A portion between 1 and 124 becomes open, and the resistance value on the open monitor 17 shows a very large value or infinity.
以」二説明したように本発明はLSIのテスト時に入出
力端子及び電源端子にテスト用の探針を位置決めする際
、前記入出力及び電源端子とは別に設けた位置決め端子
に位置決め探針を外部モニターで正確に合せることによ
り、全体の探針の端子に対する位置決めを正確かつ容易
に行えるという効果がある。As explained above, the present invention enables the positioning probe to be externally positioned at the positioning terminal provided separately from the input/output and power supply terminals when positioning the test probe at the input/output terminal and the power supply terminal during LSI testing. Accurate alignment using a monitor has the effect of accurately and easily positioning the entire probe relative to the terminal.
第1図は本発明の実施例を示す図である。 FIG. 1 is a diagram showing an embodiment of the present invention.
Claims (1)
互いに接続されている位置決め端子を通常の入出力端子
及び電源端子とは別個に有することを特徴とする集積回
路。(1) An integrated circuit characterized by having positioning terminals, some of which are connected to each other via wiring patterns within the integrated circuit chip, separate from normal input/output terminals and power supply terminals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62289075A JPH01129432A (en) | 1987-11-16 | 1987-11-16 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62289075A JPH01129432A (en) | 1987-11-16 | 1987-11-16 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01129432A true JPH01129432A (en) | 1989-05-22 |
Family
ID=17738499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62289075A Pending JPH01129432A (en) | 1987-11-16 | 1987-11-16 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01129432A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03196633A (en) * | 1989-12-26 | 1991-08-28 | Fuji Electric Co Ltd | Semiconductor integrated circuit device and semiconductor wafer |
JP2006222147A (en) * | 2005-02-08 | 2006-08-24 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
WO2007055012A1 (en) * | 2005-11-10 | 2007-05-18 | Nhk Spring Co., Ltd. | Contact unit and testing system |
US8404496B2 (en) | 1999-11-11 | 2013-03-26 | Fujitsu Semiconductor Limited | Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state |
CN117665544A (en) * | 2024-02-01 | 2024-03-08 | 合肥晶合集成电路股份有限公司 | Wafer acceptance test method |
-
1987
- 1987-11-16 JP JP62289075A patent/JPH01129432A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03196633A (en) * | 1989-12-26 | 1991-08-28 | Fuji Electric Co Ltd | Semiconductor integrated circuit device and semiconductor wafer |
US8404496B2 (en) | 1999-11-11 | 2013-03-26 | Fujitsu Semiconductor Limited | Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state |
US8759119B2 (en) | 1999-11-11 | 2014-06-24 | Fujitsu Semiconductor Limited | Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state |
JP2006222147A (en) * | 2005-02-08 | 2006-08-24 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
WO2007055012A1 (en) * | 2005-11-10 | 2007-05-18 | Nhk Spring Co., Ltd. | Contact unit and testing system |
CN117665544A (en) * | 2024-02-01 | 2024-03-08 | 合肥晶合集成电路股份有限公司 | Wafer acceptance test method |
CN117665544B (en) * | 2024-02-01 | 2024-06-11 | 合肥晶合集成电路股份有限公司 | Wafer acceptance test method |
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