CN117665544A - Wafer acceptance test method - Google Patents
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Abstract
The invention relates to a wafer acceptance test method. The wafer acceptance test method comprises the following steps: providing a probe card and a tester; the probe card comprises a plurality of probe groups, wherein each probe group comprises more than two probes, and the tester is electrically connected with each probe group; aligning the wafer to be detected, and determining the position of each test point of the wafer to be detected; the probe groups are opposite to the test points and are needled, so that the probe groups are contacted with the test points; detecting the resistance between two probes in each probe group through a testing machine to obtain a plurality of resistance values, and judging whether the resistance values are smaller than a preset resistance threshold value or not; and if the resistance values are smaller than the preset resistance threshold value, performing wafer acceptance test through the tester. By the wafer acceptance test method provided by the invention, whether the probe set normally contacts the test point can be timely judged, the test is avoided under the condition of abnormal needle insertion, and the yield is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a wafer acceptance test method.
Background
Wafer acceptance test (Wafer Acceptance Test, WAT) is to measure electrical parameters of specific test structures by a tester after Wafer (Wafer) product flow is completed and before quality inspection to detect process conditions of each Wafer product and evaluate quality and stability of semiconductor manufacturing processes. Probe Card (Probe Card) is an important component of WAT test, and a tester is used for binding test points (pads) led out from devices (devices) on a wafer through the Probe Card so as to achieve the purposes of signal loading and measurement.
At present, after the wafer WAT test flow determines the wafer position, the probe card is moved to the selected position to be inserted into the probe card, the corresponding test structure (Testkey) is tested, and whether the inserted position is accurate or not can not be judged by the later test. After the test of a plurality of wafers is finished, the data NG (No Good) cannot be used for warning, but the test of a plurality of Wafer is finished at this time, and the probe card is damaged or the yield of the product is lost due to false pricking.
Disclosure of Invention
Based on this, it is necessary to provide a wafer acceptance test method for the problem that the probe card is damaged or the yield of the product is low because the abnormal needle insertion of the probe card is determined only by the data NG.
The invention provides a wafer acceptance test method, which comprises the following steps:
providing a probe card and a tester; the probe card comprises a plurality of probe groups, wherein each probe group comprises more than two probes, and the tester is electrically connected with each probe group;
aligning the wafer to be detected, and determining the position of each test point of the wafer to be detected;
the probe groups are opposite to the test points and are needled, so that the probe groups are contacted with the test points;
detecting the resistance between two probes in each probe group through a testing machine to obtain a plurality of resistance values, and judging whether the resistance values are smaller than a preset resistance threshold value or not;
and if the resistance values are smaller than the preset resistance threshold value, performing wafer acceptance test through the tester.
In one embodiment, the wafer acceptance test method further comprises:
and if at least one resistance value is greater than or equal to a preset resistance threshold value, sending out warning information.
In one embodiment, if at least one resistance value is greater than or equal to a preset resistance threshold, the wafer acceptance test method further includes:
lifting the probe card;
the relative positions of the probe card and the wafer to be detected are adjusted again, so that each probe set is opposite to each test point of the wafer to be detected and is needled, and each probe set is contacted with each test point;
and judging whether the resistance value between two probes in each probe group is smaller than a preset resistance threshold value or not.
In one embodiment, readjusting the relative positions of the probe card and the wafer to be inspected comprises:
determining the offset direction of the probe card relative to the wafer to be detected according to the resistance value measured by the probe set positioned at the head and the resistance value measured by the probe set positioned at the tail;
and adjusting the relative positions of the probe card and the wafer to be detected according to the offset direction.
In one embodiment, determining the offset direction of the probe card relative to the wafer to be inspected based on the resistance measured by the probe set at the head and the resistance measured by the probe set at the tail includes:
if the resistance value measured by the probe set positioned at the head part is smaller than a preset resistance threshold value and the resistance value measured by the probe set positioned at the tail part is larger than or equal to the preset resistance threshold value, judging that the probe card deviates towards the tail part relative to the wafer to be detected;
and if the resistance value measured by the probe group positioned at the head part is larger than or equal to a preset resistance threshold value and the resistance value measured by the probe group positioned at the tail part is smaller than the preset resistance threshold value, judging that the probe card deviates towards the head part relative to the wafer to be detected.
In one embodiment, aligning a wafer to be inspected, determining positions of test points of the wafer to be inspected includes:
determining the circle center of a wafer to be detected; wherein, the center of the circle is provided with an alignment mark;
determining the position of the alignment mark;
and establishing a grid coordinate system by taking the position of the alignment mark as an origin, and determining the coordinate position of each test point.
In one embodiment, determining the center of a circle of a wafer to be inspected includes:
determining the edge of a wafer to be detected, and selecting any three points on the edge;
and determining the circle center of the wafer to be detected through the selected perpendicular bisectors of the connecting lines among the three points.
In one embodiment, determining the location of the alignment mark includes:
adjusting the magnification of the microscope to be a first magnification, and determining the position of the alignment mark through the microscope;
and adjusting the magnification of the microscope to be a second magnification which is larger than the first magnification, and adjusting the position relation between the alignment mark and the alignment mark of the microscope to align the alignment mark with the alignment mark of the microscope.
In one embodiment, the number of wires electrically connected to each probe set by the tester is equal to the number of probes, and the wires are connected to the probes one by one.
In one embodiment, the distance between adjacent probes in the probe set is less than the width of the test site.
In the wafer test method, the probe card comprises a plurality of probe groups, each probe group comprises a plurality of probes, after the wafer to be tested is aligned, the probe card is inserted into the probe group to enable the probe group to be in contact with the test point, and a plurality of probes of the same probe group are in contact with the same test point. And testing the resistance between the two probes of the same probe group by using a testing machine, and if the resistance value is smaller than a preset resistance threshold value, considering that the two probes are contacted with the same test point, wherein the test point is conductive, so that the two probes are conducted. And then, performing wafer acceptance test including electrical property, function and reliability test by a tester. In the prior art, the probe card only has one probe, can not judge whether the test point is accurately penetrated, can only judge by reading the test data of the tester, and has certain hysteresis. By the wafer acceptance test method provided by the invention, whether the probe set normally contacts the test point can be timely judged, abnormal test is avoided, and the yield is improved.
Drawings
FIG. 1 is a schematic diagram of a test structure of a wafer;
FIG. 2 is a schematic illustration of the insertion of a probe card;
FIG. 3 is a diagram showing a comparison of probe card needle sticks normally and needle sticks abnormally;
FIG. 4 is a flow chart of a method of wafer acceptance testing in one embodiment;
FIG. 5 is a schematic diagram of the structure of a probe card in one embodiment;
FIG. 6 is a schematic diagram of connection of a tester under test in one embodiment;
FIG. 7 is a flow chart of a method of wafer acceptance testing in another embodiment;
FIG. 8 is a schematic diagram of a method for determining the center of a circle of a wafer to be inspected at three points in one embodiment.
Reference numerals illustrate:
10. a test structure; 11. a device; 12. a test point; 20. a probe card; 21. a probe; 22. a probe set; 30. a testing machine; 31. and (5) conducting wires.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "first," "second," "third," or "third" may explicitly or implicitly include one or at least two such features, with "one end" and "another end" and "proximal end" and "distal end" generally referring to the respective two portions, including not only the endpoints, but also the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, e.g., as being either a fixed connection, a removable connection, or as being integral therewith; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements.
Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
WAT testing is a wafer acceptance test, and WAT is a critical test link in integrated circuit fabrication for verifying and evaluating the quality and performance of chips on a wafer. Typically, a test structure (Testkey) of a wafer is tested by a tester. The WAT tester is an automated test device for performing various tests during a wafer acceptance test, and can rapidly and accurately test the electrical characteristics, functions, reliability, etc. of chips on the whole wafer under a high throughput condition, so that the tester can detect the device 11 after connecting the test points through a probe card.
Referring to fig. 1, fig. 1 shows a schematic diagram of a test structure 10 of a wafer, wherein the test structure 10 includes a Device 11 and a test point 12 (Pad), the test point 12 being electrically connected to the Device 11 and being a lead wire led out from the Device 11 for connection to an external tester.
Referring to fig. 2, fig. 2 shows a schematic view of a conventional probe card 20, wherein the probe card 20 has a plurality of probes 21, and when testing a test structure 10, the probe card 20 is inserted, so that the probes 21 on the probe card 20 are connected with a test point 12 for signal loading and measurement purposes. Illustratively, the test structure 10 shown in FIG. 2 includes 20 test points 12, and in practice the number of test points 12 may be less or more than 20. The probe card 20 includes 20 probes, each probe 21 is inserted into a test site 12, and a tester is connected to the probes 21 to test the device 11.
After the probe card is inserted into the probe card in a normal state, the probe contacts with the test point 12, however, in the actual test process, the probe card is abnormally inserted out of the test point 12 of the device 11 due to an alignment error or communication abnormality, resulting in measurement abnormality, as shown in fig. 3.
Referring to fig. 4, fig. 4 is a flowchart illustrating a wafer acceptance test method according to an embodiment of the invention, and the wafer acceptance test method according to an embodiment of the invention includes the following steps S402 to S410:
s402, providing a probe card and a tester; the probe card comprises a plurality of probe groups, wherein each probe group comprises more than two probes, and the tester is electrically connected with each probe group.
Referring to fig. 5, fig. 5 shows a schematic diagram of the structure of probe card 20 in one embodiment. The probe card 20 includes a plurality of probe groups 22, each probe group 22 including at least two probes 21, it being understood that each probe group 22 may include two or more probes 21. Schematically, only two probes 21, pin a and pin b, respectively, are included in fig. 5, and in practice the probes 21 may also have three or more.
Illustratively, in FIG. 5, the number of test sites 12 is 20, the number of probe sets 22 is 20, and the number of probe sets 22 is the same as the number of test sites 12 from the pin1 set, the pin2 set to the pin20 set, respectively. In practice, the number of pads may be less than or more than 20, and the number of probe sets 22 may be less than or more than 20, which is not limited in this embodiment.
Referring to fig. 6, fig. 6 illustrates a schematic diagram of the connection of tester 30 to test structure 10 in one embodiment. Wherein the tester 30 is connected to the probe card 20, and the probe card 20 is connected to the pad of the test structure 10 through the probe set 22. In one embodiment, the number of wires 31 electrically connected to each probe set 22 by tester 30 is equal to the number of probes 21, and wires 31 are connected to probes 21 one by one. In this way, the tester 30 can electrically control each probe 21 of the probe group 22, such as applying a voltage, a current, or the like. Illustratively, the leads 31 may also be probe structures.
S404, aligning the wafer to be detected, and determining the positions of all test points of the wafer to be detected.
Wherein the wafer to be inspected is a target inspection wafer, and the tester 30 is connected to the test structure 10 of the wafer to be inspected to inspect the device 11.
Alignment refers to determining the position of the test structure 10 of the wafer to be inspected, and thus the position of the test point 12.
S406, the probe groups are opposite to the test points and are inserted into the test points, so that the probe groups are contacted with the test points.
Wherein the probe card 20 is opposite the test structure 10 and each probe set 22 on the probe card 20 is opposite a test site 12 on the test structure 10.
The penetration means controlling the probe card 20 to move toward the test structure, and the plurality of probes 21 on one probe set 22 penetrate into the same test point 12 to contact the test point 12 when the probe set 22 is positioned opposite to the test point 12.
In one possible implementation, the distance between adjacent probes 21 in a probe set 22 is less than the width of a test site 12, so that all probes 21 of the same probe set 22 can contact the same test site.
S408, detecting the resistance between two probes in each probe set by using a testing machine to obtain a plurality of resistance values, and judging whether the resistance value is smaller than a preset resistance threshold value.
Each probe set 22 has a plurality of probes 21, and the plurality of probes 21 of the same set are inserted into the same test site 12 with the insertion of the probe card 20. Since the test point 12 is conductive, if the plurality of probes 21 are normally inserted into the test point 12, the plurality of probes 21 are conducted, and a voltage is applied to the probes 21 by the tester 30 to generate a loop current, so that the resistance value between the probes 21 can be calculated according to the ratio of the voltage and the current.
If the probes 21 do not contact the test points 12, but instead penetrate into abnormal locations, such as other areas of the test structure 10, which if not conductive, then the two probes 21 are disconnected, and the resistance value is considered to be infinite; the resistance of this region, if conductive, will also vary from the resistance of test point 12.
And S410, if the resistance values are smaller than the preset resistance threshold value, performing wafer acceptance test through a tester.
And judging the calculated resistance value, and if the calculated resistance value is smaller than the preset resistance threshold value, considering that the probe group 22 is in contact with the test point 12, and testing normally. Illustratively, the preset resistance threshold may be 1000 ohms. If the calculated resistance value of each probe set 22 is less than the predetermined resistance threshold, then the probe card 20 is considered successful in probing, and the tester 30 can perform wafer acceptance tests such as electrical characteristics, functions, and reliability tests.
In the wafer receiving test method, the probe card 20 includes a plurality of probe groups 22, and each probe group 22 includes a plurality of probes 21, and after the wafer to be tested is aligned, the probe card 20 is inserted into the probe group 22 to contact with the test point 12, and the plurality of probes 21 of the same probe group 22 contact with the same test point 12. The resistance between two probes 21 of the same probe set 22 is tested by the tester 30, and if the resistance value is smaller than the preset resistance threshold, the two probes 21 are considered to be in contact with the same test point 12, because the test point 12 is conductive, so that conduction between the two probes 21 is achieved. The wafer is then subjected to testing by the tester 30, including electrical characteristics, functional and reliability testing, and the like. The probe card 20 in the conventional technology has only one probe 21, and cannot determine whether to accurately insert the test point 12, but can determine by reading the test data of the tester 30, and has a certain hysteresis. By the wafer acceptance test method provided by the invention, whether the probe set 22 normally contacts with the test point can be timely judged, abnormal test is avoided, and the yield is improved.
In an exemplary embodiment, the wafer acceptance test method further includes: and if at least one resistance value is greater than or equal to a preset resistance threshold value, sending out warning information.
If the resistance value measured by one of the probe sets 22 is greater than or equal to the preset resistance threshold, the probe set 22 is considered to be not inserted into the test point 12 accurately, but is inserted into the non-test point 12 abnormally, and then warning information is sent out.
The alert information may illustratively be audible, visual or audible and visual information. In one possible implementation, an Early Alarm is displayed on tester 30. Optionally, a warning message can be sent out through a buzzer.
In this embodiment, if at least one resistance value is greater than or equal to the preset resistance threshold, it is considered that part of the probe sets 22 of the probe card 20 fail to normally contact with the test points 12, and at this time, a warning message is sent to prompt to judge abnormality in time.
In an exemplary embodiment, if at least one resistance value is greater than or equal to a preset resistance threshold, the wafer acceptance test method further includes: lifting the probe card; the relative positions of the probe card and the wafer to be detected are adjusted again, so that each probe set is opposite to each test point of the wafer to be detected and is needled, and each probe set is contacted with each test point; and judging whether the resistance value between two probes in each probe group is smaller than a preset resistance threshold value or not.
If at least one resistance value is greater than or equal to the preset resistance threshold, the probe card 20 is considered to fail to puncture, and a re-puncture is required. Lifting the probe card 20 to separate the probe groups 22 from the test structure 10, adjusting the relative positions of the probe card 20 and the wafer to be detected, and puncturing again to enable each probe group to be in contact with each test point; and judging whether the resistance value between two probes in each probe group is smaller than a preset resistance threshold value or not. If the resistance values are smaller than the preset resistance threshold value, the needle insertion is considered to be successful, and the wafer is subjected to the test by the tester; if at least one resistance value is larger than or equal to the preset resistance threshold, the needle insertion is considered to be failed, and warning information is sent out, so that the needle insertion is detected again after position adjustment. If the puncture fails again, the position can be adjusted again until the puncture is successful.
Referring to fig. 7, fig. 7 shows a flowchart of a wafer acceptance test method in one embodiment, including the following steps S702 to S714:
s702, providing a probe card and a tester; the probe card comprises a plurality of probe groups, wherein each probe group comprises more than two probes, and the tester is electrically connected with each probe group.
S704, aligning the wafer to be detected, and determining the positions of all test points of the wafer to be detected.
S706, the probe groups are opposite to the test points and are inserted into the test points, so that the probe groups are contacted with the test points.
S708, detecting the resistance between two probes in each probe set by a tester to obtain a plurality of resistance values.
S710, judging whether the resistance value is smaller than a preset resistance threshold.
And S712, if the resistance values are smaller than the preset resistance threshold value, performing wafer acceptance test by a tester.
And S714, if at least one resistance value is greater than or equal to a preset resistance threshold value, sending out warning information, lifting the probe card, and adjusting the relative positions of the probe card and the wafer to be detected again to enable each probe set to be opposite to each test point of the wafer to be detected.
In this embodiment, if at least one resistance value is greater than or equal to the preset resistance threshold, the probe card 20 is considered to fail to be inserted, after warning information is sent, the probe card is lifted up, the relative positions of the probe card 20 and the test structure 10 are adjusted again, so that each probe set is opposite to each test point of the wafer to be tested, and the next resistance value detection of the probe set 20 is performed. In this way, besides the traditional positioning mode, the electrical judgment of the once-through resistance value is added, whether the probe card 20 is successfully inserted into the needle is determined in time, the test is still performed after the abnormal insertion is avoided, and the product yield is improved.
In one exemplary embodiment, readjusting the relative positions of the probe card and the wafer to be inspected includes: determining the offset direction of the probe card relative to the wafer to be detected according to the resistance value measured by the probe set positioned at the head and the resistance value measured by the probe set positioned at the tail; and adjusting the relative positions of the probe card and the wafer to be detected according to the offset direction.
Where the header refers to the first probe group 22 of the probe card 20, such as pin1 group in fig. 5, and the tail refers to the last probe group 22 of the probe card 20, such as pin20 group in fig. 5. The offset direction of the probe card 20 relative to the test structure 10 is determined by testing the resistance values of the head and tail portions, so that the probe card 20 and the test structure 10 can be aligned by adjusting in the opposite direction of the offset direction.
If the resistance value measured by the probe set 22 at the head is smaller than the preset resistance threshold and the resistance value measured by the probe set 22 at the tail is greater than or equal to the preset resistance threshold, it is determined that the probe card 20 is shifted toward the tail with respect to the wafer to be inspected, and as an example, fig. 5 shows that the probe card 20 is shifted rightward with respect to the wafer to be inspected.
If the resistance of the leading probe set 22 is less than the predetermined resistance threshold, then the leading probe set 22 is considered to be stuck in the test point 12, while the trailing probe set 22 is not inserted into the test point 12. At this time, the entire probe card 20 may move right, the pin1 group is inserted into the pad2, the pin2 group is inserted into the pad3, and so on, the pin20 group is abnormally inserted, so that the resistance value is greater than the preset resistance threshold.
And if the resistance value measured by the probe group positioned at the head part is larger than or equal to a preset resistance threshold value and the resistance value measured by the probe group positioned at the tail part is smaller than the preset resistance threshold value, judging that the probe card deviates towards the head part relative to the wafer to be detected.
Similarly, if the resistance of the trailing set of probes 22 is less than the predetermined resistance threshold, then the trailing set of probes 22 is considered to be stuck into the test site 12, while the leading set of probes 22 is not stuck into the test site 12. It is possible that pin20 group inserts pad19 and pin1 group is inserted abnormally, and at this time, probe card 20 is offset toward the head with respect to the wafer to be inspected, and, for example, probe card 20 is offset leftward with respect to the wafer to be inspected, as shown in fig. 5.
In one exemplary embodiment, aligning a wafer to be inspected, determining test point locations of the wafer to be inspected, includes: determining the circle center of a wafer to be detected; wherein, the center of the circle is provided with an alignment mark; determining the position of the alignment mark; and establishing a grid coordinate system by taking the position of the alignment mark as an origin, and determining the coordinate position of each test point.
Wherein the alignment mark is a special mark for alignment, and illustratively, the alignment mark may be a cross mark.
With the alignment marks as origins, a cross coordinate system is established so that any point on the wafer can be represented in coordinates, including the position of each test point 12. The test points 12 are indicated by coordinates, and each probe group 22 of the probe card 20 is inserted with the corresponding coordinate of the test point 12 as a target insertion position.
In one possible implementation, the circle center of the wafer to be detected is determined by a three-point method, and the steps include: determining the edge of a wafer to be detected, and selecting any three points on the edge; and determining the circle center of the wafer to be detected through the selected perpendicular bisectors of the connecting lines among the three points.
As shown in fig. 8, fig. 8 illustrates a method of determining the center of a circle of a wafer to be inspected by a three-point method. The method comprises the steps of firstly determining the edge of a wafer to be detected, randomly selecting three points on the edge, connecting the two points to obtain two line segments, and making a perpendicular bisector of the two line segments, wherein the intersection point of the two perpendicular bisectors is used as the circle center of the wafer to be detected.
In one exemplary embodiment, determining the location of the alignment mark includes: adjusting the magnification of the microscope to be a first magnification, and determining the position of the alignment mark through the microscope; and adjusting the magnification of the microscope to be a second magnification which is larger than the first magnification, and adjusting the position relation between the alignment mark and the alignment mark of the microscope to align the alignment mark with the alignment mark of the microscope.
The first multiplying power is smaller multiplying power to determine the approximate position of the alignment mark. The second multiplying power is larger multiplying power to accurately determine the position of the alignment mark.
The alignment of the alignment center of the microscope and the alignment mark means that the center of the microscope coincides with the center of the alignment mark, so that the accurate position of the alignment mark can be determined, and then a grid coordinate system is established by taking the position of the alignment mark as an origin, so as to determine the coordinate position of each test point 12.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method for wafer acceptance testing, the method comprising:
providing a probe card and a tester; the probe card comprises a plurality of probe groups, wherein the probe groups comprise more than two probes, and the tester is electrically connected with each probe group;
aligning a wafer to be detected, and determining the position of each test point of the wafer to be detected;
the probe groups are opposite to the test points and are needled, so that the probe groups are contacted with the test points;
detecting the resistance between two probes in each probe set through the testing machine to obtain a plurality of resistance values, and judging whether the resistance values are smaller than a preset resistance threshold value or not;
and if the resistance values are smaller than the preset resistance threshold value, carrying out wafer acceptance test by the tester.
2. The wafer acceptance test method of claim 1, further comprising:
and if at least one resistance value is larger than or equal to the preset resistance threshold value, sending out warning information.
3. The method of claim 2, wherein if at least one of the resistance values is greater than or equal to the predetermined resistance threshold, the method further comprises:
lifting the probe card;
the relative positions of the probe card and the wafer to be detected are adjusted again, so that each probe set is opposite to each test point of the wafer to be detected and is needled, and each probe set is contacted with each test point;
and judging whether the resistance value between two probes in each probe group is smaller than a preset resistance threshold value or not.
4. The method of claim 3, wherein readjusting the relative positions of the probe card and the wafer to be inspected comprises:
determining the offset direction of the probe card relative to the wafer to be detected according to the resistance value measured by the probe set positioned at the head part and the resistance value measured by the probe set positioned at the tail part;
and adjusting the relative positions of the probe card and the wafer to be detected according to the offset direction.
5. The method according to claim 4, wherein determining the offset direction of the probe card with respect to the wafer to be inspected based on the resistance measured by the probe group at the head and the resistance measured by the probe group at the tail comprises:
if the resistance value measured by the probe set positioned at the head part is smaller than a preset resistance threshold value and the resistance value measured by the probe set positioned at the tail part is larger than or equal to the preset resistance threshold value, judging that the probe card deviates towards the tail part relative to the wafer to be detected;
and if the resistance value measured by the probe group positioned at the head part is larger than or equal to a preset resistance threshold value and the resistance value measured by the probe group positioned at the tail part is smaller than the preset resistance threshold value, judging that the probe card deviates towards the head part relative to the wafer to be detected.
6. The wafer acceptance test method of claim 1, wherein said aligning a wafer to be tested, determining each test point location of said wafer to be tested, comprises:
determining the circle center of the wafer to be detected; wherein, the circle center is provided with an alignment mark;
determining the position of the alignment mark;
and establishing a grid coordinate system by taking the position of the alignment mark as an origin, and determining the coordinate position of each test point.
7. The method for wafer acceptance test of claim 6, wherein said determining the center of the circle of the wafer to be inspected comprises:
determining the edge of the wafer to be detected, and selecting any three points on the edge;
and determining the circle center of the wafer to be detected through the selected perpendicular bisectors of the connecting lines among the three points.
8. The wafer acceptance test method of claim 6 or 7, wherein said determining the position of the alignment mark comprises:
adjusting the magnification of a microscope to be a first magnification, and determining the position of the alignment mark through the microscope;
and adjusting the magnification of the microscope to be a second magnification which is larger than the first magnification, and adjusting the position relation between the alignment mark and the alignment mark of the microscope to align the alignment mark of the microscope and the alignment mark.
9. The wafer acceptance test method of claim 1, wherein the number of wires electrically connected to each of said probe groups by said tester is equal to the number of said probes, and said wires are connected to said probes one by one.
10. The method of claim 1, wherein a distance between adjacent probes in the probe set is less than a width of the test point.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
| CN117949706A (en) * | 2024-03-21 | 2024-04-30 | 苏州珂晶达电子有限公司 | Wafer detection system, method and storage medium |
| CN111293048B (en) * | 2018-12-07 | 2024-07-02 | 紫光同芯微电子有限公司 | Wafer testing system and method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01129432A (en) * | 1987-11-16 | 1989-05-22 | Nec Corp | Integrated circuit |
| JPH07244105A (en) * | 1994-03-04 | 1995-09-19 | Hioki Ee Corp | Bridged solder detecting method by board inspecting device for mounting board |
| JPH10270511A (en) * | 1997-03-27 | 1998-10-09 | New Japan Radio Co Ltd | Wafer probe test method and wafer or dice |
| JP2008151954A (en) * | 2006-12-15 | 2008-07-03 | Sony Corp | Method of manufacturing display device, and display device |
| CN101907657A (en) * | 2010-06-11 | 2010-12-08 | 上海宏力半导体制造有限公司 | Detection method for probe resistance |
| US20130135001A1 (en) * | 2011-11-29 | 2013-05-30 | Formfactor, Inc. | Hybrid Electrical Contactor |
| CN103293503A (en) * | 2013-05-24 | 2013-09-11 | 上海宏力半导体制造有限公司 | Probe card detecting method |
| JP2015194459A (en) * | 2014-03-25 | 2015-11-05 | シャープ株式会社 | Substrate inspection probe unit and substrate inspection method |
| CN107561319A (en) * | 2017-08-23 | 2018-01-09 | 上海华力微电子有限公司 | A kind of clear needle method of WAT boards probe card |
| CN111312134A (en) * | 2020-04-02 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Detection equipment for display panel |
| CN114420619A (en) * | 2022-03-30 | 2022-04-29 | 晶芯成(北京)科技有限公司 | Wafer alignment device and method, and wafer testing method |
| CN114859087A (en) * | 2022-05-27 | 2022-08-05 | 苏州海光芯创光电科技股份有限公司 | Wafer probe card and wafer detection equipment |
-
2024
- 2024-02-01 CN CN202410139830.6A patent/CN117665544B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01129432A (en) * | 1987-11-16 | 1989-05-22 | Nec Corp | Integrated circuit |
| JPH07244105A (en) * | 1994-03-04 | 1995-09-19 | Hioki Ee Corp | Bridged solder detecting method by board inspecting device for mounting board |
| JPH10270511A (en) * | 1997-03-27 | 1998-10-09 | New Japan Radio Co Ltd | Wafer probe test method and wafer or dice |
| JP2008151954A (en) * | 2006-12-15 | 2008-07-03 | Sony Corp | Method of manufacturing display device, and display device |
| CN101907657A (en) * | 2010-06-11 | 2010-12-08 | 上海宏力半导体制造有限公司 | Detection method for probe resistance |
| US20130135001A1 (en) * | 2011-11-29 | 2013-05-30 | Formfactor, Inc. | Hybrid Electrical Contactor |
| CN103293503A (en) * | 2013-05-24 | 2013-09-11 | 上海宏力半导体制造有限公司 | Probe card detecting method |
| JP2015194459A (en) * | 2014-03-25 | 2015-11-05 | シャープ株式会社 | Substrate inspection probe unit and substrate inspection method |
| CN107561319A (en) * | 2017-08-23 | 2018-01-09 | 上海华力微电子有限公司 | A kind of clear needle method of WAT boards probe card |
| CN111312134A (en) * | 2020-04-02 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Detection equipment for display panel |
| CN114420619A (en) * | 2022-03-30 | 2022-04-29 | 晶芯成(北京)科技有限公司 | Wafer alignment device and method, and wafer testing method |
| CN114859087A (en) * | 2022-05-27 | 2022-08-05 | 苏州海光芯创光电科技股份有限公司 | Wafer probe card and wafer detection equipment |
Non-Patent Citations (1)
| Title |
|---|
| 张鹏辉: "圆片测试中探针接触电阻的影响与改善方法", 《电子与封装》, vol. 18, no. 1, 31 January 2018 (2018-01-31), pages 8 - 11 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
| CN111293048B (en) * | 2018-12-07 | 2024-07-02 | 紫光同芯微电子有限公司 | Wafer testing system and method thereof |
| CN117949706A (en) * | 2024-03-21 | 2024-04-30 | 苏州珂晶达电子有限公司 | Wafer detection system, method and storage medium |
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|---|---|
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