CN117949706A - Wafer detection system, method and storage medium - Google Patents
Wafer detection system, method and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a wafer detection system, a wafer detection method and a storage medium, and relates to the technical field of wafer detection. The wafer detection system comprises an automatic probe station, an upper computer and a wafer detection device; the upper computer generates an operation instruction and a first detection instruction; the automatic probe station connects the positions to be detected of the wafers to be detected on the automatic probe station according to the operation instructions; the wafer detection device determines the connection state of the probe of the automatic probe station and the position to be detected of the wafer to be detected according to the first detection instruction; the upper computer generates a second detection instruction and a third detection instruction according to the connection state, the wafer detection device configures a wafer to be detected according to the second detection instruction, and the wafer detection device detects the wafer to be detected according to the third detection instruction and generates a detection result; and the upper computer analyzes the detection result, draws a wafer defect map and generates a wafer defect analysis report. The method and the device can provide comprehensive and effective data for an improvement scheme for improving the yield of the wafer production line.
Description
Technical Field
The embodiment of the invention relates to the technical field of wafer detection, in particular to a wafer detection system, a wafer detection method and a storage medium.
Background
Theoretical reasoning analysis on the related problem points of the wafer is relatively mature, for example, how to infer the variation and defect of the process links of the process through wafer error distribution, and infer the design radiation effect, the related index of the design material and the like through data address errors. There is no more mature solution on the market at present for determining the wafer errors in an omnibearing manner and effectively positioning the wafer errors.
Currently, in the problem positioning process of developing a semiconductor wafer production line, a synchronous SRAM is generally used to detect the yield of the wafer production line, and then a universal tester is used to program preset write data of each period to perform a functional test on the produced wafer. However, the general testing machine has low flexibility in the way of programming preset write data and limited preset write data capacity, and generally can only perform simple read-write, and cannot cover the common March algorithm. In addition, the general tester cannot analyze the wafer defects in a full-scale manner, so that effective data cannot be provided for an improvement scheme for improving the yield of a wafer production line.
Disclosure of Invention
The embodiment of the invention provides a wafer detection system, a method and a storage medium, which are used for realizing the test of any March algorithm on a wafer, further generating a wafer defect analysis report by combining wafer defect coordinates and wafer defects, and providing comprehensive and effective data for an improved scheme for improving the yield of a wafer production line.
In a first aspect, an embodiment of the present invention provides a wafer inspection system, including an automatic probe station, an upper computer, and a wafer inspection device;
The automatic probe station and the wafer detection device are connected with the upper computer, and the automatic probe station is connected with the wafer detection device;
the upper computer is used for generating an operation instruction and a first detection instruction;
The automatic probe station is used for connecting the position to be detected of the wafer to be detected on the automatic probe station according to the operation instruction; the wafer detection device is used for determining the connection state of the probe of the automatic probe station and the position to be detected of the wafer to be detected according to the first detection instruction; the upper computer is used for generating a second detection instruction and a third detection instruction according to the connection state, the wafer detection device is used for configuring the wafer to be detected according to the second detection instruction, and the wafer detection device is used for detecting the wafer to be detected according to the third detection instruction and generating a detection result; the upper computer is used for analyzing the detection result, drawing a wafer defect map and generating a wafer defect analysis report.
Optionally, the automatic probe station comprises a probe cleaning unit, a probe connecting unit, a wafer control unit and a coordinate positioning unit;
The probe cleaning unit is used for performing needle cleaning operation according to the operation instruction;
The probe connection unit is used for performing probe connection operation according to the operation instruction;
the wafer control unit is used for controlling the probe to be adjusted to a position to be detected according to the operation instruction;
The coordinate positioning unit is used for determining the coordinate of the detection position according to the operation instruction.
Optionally, the wafer detection device comprises a programmable memory detection unit, a soft core, an open-short circuit test control unit, a clock signal generation unit and a communication unit;
The soft core is used for acquiring the first detection instruction through the communication unit, and the open-short circuit test control unit is used for determining the connection state of the probe and the position to be detected of the wafer to be detected according to the first detection instruction; the soft core is further used for acquiring a second detection instruction and a third detection instruction through the communication unit according to the connection state, the clock signal generating unit is used for generating a clock signal according to the second detection instruction, and the soft core is used for configuring the wafer to be detected according to the clock signal; the programmable memory detection unit is used for detecting the wafer to be detected according to the third detection instruction and obtaining a detection result.
Optionally, the clock signal generation unit comprises a dynamic/static clock generation subunit;
the dynamic/static clock generation subunit is used for generating a clock signal, and the soft core is used for configuring the scanning voltage and the scanning frequency of the wafer to be detected according to the clock signal.
Optionally, the wafer inspection device further includes an inspection result storage unit;
the detection result storage unit is used for storing the detection result and sending the detection result to the upper computer through the communication unit.
Optionally, the upper computer comprises a wafer detection configuration unit to be detected, an automatic probe station control unit and an algorithm regression control unit;
The automatic probe station control unit is used for generating the operation instruction and the first detection instruction;
The wafer detection configuration unit to be detected is used for generating the second detection instruction;
The algorithm regression control unit is used for generating the third detection instruction.
Optionally, the wafer to be tested detection configuration unit includes a voltage configuration subunit and a voltage monitoring subunit;
The second detection instruction comprises a voltage adjustment instruction and a voltage acquisition instruction; the voltage configuration subunit is used for generating a voltage adjustment instruction, and the voltage monitoring subunit is used for generating a voltage acquisition instruction.
Optionally, the upper computer further comprises a first data processing unit and a second data processing unit;
The first data processing unit is used for receiving the detection result and preprocessing the detection result;
The second data processing unit is used for drawing a defect bitmap for the preprocessed detection result and the coordinates of the position to be detected, and splicing the defect bitmap to obtain a wafer defect map;
the second data processing unit is further used for analyzing the detection result after pretreatment and generating a wafer defect analysis report.
In a second aspect, an embodiment of the present invention further provides a wafer inspection method, which is performed by the wafer inspection system provided by any embodiment of the present invention, where the wafer inspection method includes:
the upper computer generates an operation instruction and a first detection instruction;
the automatic probe station connects the position to be detected of the wafer to be detected on the automatic probe station according to the operation instruction;
the wafer detection device determines the connection state of the probe of the automatic probe station and the position to be detected of the wafer according to the first detection instruction;
The upper computer generates a second detection instruction and a third detection instruction according to the connection state;
the wafer detection device configures the wafer to be detected according to the second detection instruction;
the wafer detection device detects the wafer to be detected according to the third detection instruction and generates a detection result;
and the upper computer analyzes the detection result, draws a wafer defect map and generates a wafer defect analysis report.
In a third aspect, an embodiment of the present invention further provides a computer readable storage medium storing a computer program, where the computer program when executed by a processor implements a wafer inspection method according to any embodiment of the present invention.
The upper computer of the wafer detection system provided by the embodiment of the invention can coordinate the automatic probe station to be matched with the wafer detection device to realize the test of any March algorithm on the wafer to be detected, and generate a detection result. The upper computer can also acquire the position to be detected of the wafer to be detected through the automatic probe station, acquire the detection result through the wafer detection device, and draw a wafer defect map and a wafer defect analysis report according to the position to be detected of the wafer to be detected and the detection result. Therefore, the method and the device can realize the test of any March algorithm on the wafer, further combine the wafer defect coordinates and the wafer defects to generate a wafer defect analysis report, and provide comprehensive and effective data for the improvement scheme for improving the yield of the wafer production line.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a wafer inspection system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another exemplary wafer inspection system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another exemplary embodiment of a wafer inspection apparatus;
fig. 4 is a flow chart of a wafer inspection method according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Because the manufacturing and packaging steps of the wafer are long and complex, and the related process nodes of the wafer manufacturing and packaging cannot be perfect in both initial research and development and mature use, the improvement and control of the wafer yield are particularly important, and the wafer yield has a significant influence on the cost of the product. In this regard, the embodiment of the invention provides a wafer detection system, which can realize the test of any March algorithm on a wafer, further generate a wafer defect analysis report by combining the wafer defect coordinates and the wafer defects, and provide comprehensive and effective data for an improved scheme for improving the yield of a wafer production line.
Fig. 1 is a schematic structural diagram of a wafer inspection system according to an embodiment of the present invention, and as shown in fig. 1, the wafer inspection system includes an automatic probe station 10, an upper computer 20, and a wafer inspection device 30; the automatic probe station 10 and the wafer detection device 30 are connected with the upper computer 20, and the automatic probe station 10 is connected with the wafer detection device 30;
The upper computer 20 is used for generating an operation instruction and a first detection instruction; the automatic probe station 10 is used for connecting the position to be detected of the wafer to be detected on the automatic probe station 10 according to the operation instruction; the wafer inspection device 30 is configured to determine a connection state between the probe of the automatic probe station 10 and a position to be inspected of the wafer to be inspected according to the first inspection instruction; the upper computer 20 is used for generating a second detection instruction and a third detection instruction according to the connection state, the wafer detection device 30 is used for configuring a wafer to be detected according to the second detection instruction, and the wafer detection device 30 is used for detecting the wafer to be detected according to the third detection instruction and generating a detection result; the upper computer 20 is used for analyzing the detection result, drawing a wafer defect map and generating a wafer defect analysis report.
The wafer detection device 30 is an FPGA test device capable of supporting programming by any March algorithm, and constructs a microkernel capable of identifying a micro instruction by using the concept of a conventional microcontroller, and performs functional regression test of relevant conditions such as March algorithm and voltage on a wafer. Wherein the microinstruction is a binary sequence recognizable by the microkernel. The microkernel is an operation and control unit operated in a single cycle, and the microkernel mainly functions to fetch, decode and execute microinstructions in the programmable ROM. And downloading micro instruction codes corresponding to any March algorithm to the corresponding ROM through the microkernel, and analyzing the micro instruction by the microkernel to generate a corresponding address vector and a data vector, so that the wafer to be detected is tested by the March algorithm. The upper computer 20 is a control center of the whole wafer detection system, integrates data analysis and control, and can send control instructions to the automatic probe station 10 and the wafer detection device 30, so that the automatic probe station 10 is matched with the wafer detection device 30 to realize detection of wafers to be detected, and a detection result is obtained. The upper computer 20 can also perform defect analysis on the wafer according to the position to be detected and the detection result of the wafer to be detected, so as to provide comprehensive and effective data for an improvement scheme for improving the yield of the wafer production line. The automatic probe station 10 is used for placing a wafer to be inspected and provides a plurality of adjustable test probes to be matched with the wafer inspection device 30 for inspecting the wafer to be inspected.
Specifically, the wafer inspection system describes a process of inspecting a wafer to be inspected: the upper computer 20 generates an operation command and transmits the operation command to the automatic probe station 10, and the automatic probe station 10 connects the position to be detected of the wafer to be detected on the automatic probe station 10 according to the operation command. After the upper computer 20 acquires the operation instruction completion information fed back by the automatic probe station 10, a first detection instruction is generated and sent to the wafer detection device 30. The wafer inspection device 30 determines the connection state between the probe of the automatic probe station 10 and the position to be inspected of the wafer to be inspected according to the first inspection instruction, and feeds back the connection information to the upper computer 20. The upper computer 20 generates a second detection instruction and a third detection instruction according to the connection state, the wafer detection device 30 firstly configures the wafer to be detected according to the second detection instruction, then realizes the test of any March algorithm on the wafer to be detected according to the third detection instruction after the configuration of the wafer to be detected is completed, generates a detection result, and feeds back the detection result to the upper computer 20. The upper computer 20 can obtain the position to be detected of the wafer to be detected through the automatic probe station 10, obtain the detection result through the wafer detection device 30, and draw a wafer defect map and a wafer defect analysis report according to the position to be detected of the wafer to be detected and the detection result.
The upper computer 20 of the wafer detection system provided by the embodiment of the invention can coordinate the automatic probe station 10 to be matched with the wafer detection device 30 to realize the test of any March algorithm on the wafer to be detected, and generate a detection result. The upper computer 20 can also obtain the position to be detected of the wafer to be detected through the automatic probe station 10, obtain the detection result through the wafer detection device 30, and draw a wafer defect map and a wafer defect analysis report according to the position to be detected of the wafer to be detected and the detection result. Therefore, the method and the device can realize the test of any March algorithm on the wafer, further combine the wafer defect coordinates and the wafer defects to generate a wafer defect analysis report, and provide comprehensive and effective data for the improvement scheme for improving the yield of the wafer production line.
Based on the above embodiments, fig. 2 is a schematic structural diagram of another wafer inspection system according to an embodiment of the present invention. As shown in fig. 2, the automatic probe station 10 includes a probe cleaning unit 110, a probe connection unit 120, a wafer control unit 130, and a coordinate positioning unit 140;
The probe cleaning unit 110 is used for performing a probe cleaning operation according to the operation instruction; the probe connection unit 120 is used for performing probe connection operation according to the operation instruction; the wafer control unit 130 is used for controlling the probe to adjust to the position to be detected according to the operation instruction; the coordinate positioning unit 140 is used for determining the coordinates of the detection position according to the operation instruction.
The automatic probe station 10 is matched with the wafer detection device 30 to complete the related actions of jump of the DIE position (position to be detected), connection by needle insertion, needle cleaning and the like in the test process. In addition, it is also necessary to record the coordinates of each jump of the DIE position (position to be detected) and feed back the coordinates of each jump of the DIE position (position to be detected) to the host computer 20.
Optionally, with continued reference to fig. 2, the wafer inspection apparatus 30 includes a programmable memory inspection unit 310, a soft core 320, an open-circuit test control unit 330, a clock signal generation unit 340, and a communication unit 350;
The soft core 320 is configured to obtain a first detection instruction through the communication unit 350, and the open-short test control unit 330 is configured to determine a connection state between the probe and a position to be detected of the wafer to be detected according to the first detection instruction; the soft core 320 is further configured to obtain a second detection instruction and a third detection instruction through the communication unit 350 according to the connection state, the clock signal generating unit 340 is configured to generate a clock signal according to the second detection instruction, and the soft core 320 is configured to configure a wafer to be detected according to the clock signal; the programmable memory inspection unit 310 is configured to inspect the wafer to be inspected according to the third inspection instruction, and obtain an inspection result.
Wherein, the soft core 320 can realize interaction with external serial logic and control over serial interface devices, and the soft core 320 is a Microblaze soft core 321 embedded in xlinx. The open-circuit test control unit 330 may detect the connection state of the probe and the position to be detected of the wafer to be detected, so that the wafer to be detected may be tested by any March algorithm under the condition that the connection of the probe and the position to be detected of the wafer to be detected is confirmed to be qualified. The communication unit 350 is a bridge that performs information interaction with the upper computer 20, and may transmit an instruction sent by the upper computer 20 to the soft core 320, or send a detection result of detecting a wafer to be detected by the programmable memory detection unit 310 to the upper computer 20. Illustratively, the communication unit 350 includes gigabit ethernet 351 transmission circuitry to accommodate high-speed read/write error data transmission and command interaction.
The clock signal generation unit 340 includes a dynamic/static clock generation subunit; the dynamic/static clock generation subunit is configured to generate a clock signal, and the soft core 320 is configured to configure a scan voltage and a scan frequency of a wafer to be inspected according to the clock signal.
Wherein the dynamic/static clock generation subunit is a Xilinx fpga-based mixed mode clock manager, and can be dynamically reconfigured by AXI4-Lite 327 to generate any frequency and phase within 800 Mhz.
Optionally, with continued reference to fig. 2, the wafer inspection apparatus 30 further includes an inspection result storage unit 360; the detection result storage unit 360 is used for storing the detection result and transmitting the detection result to the host computer 20 through the communication unit 350.
The programmable memory detecting unit 310 stores the generated detection result in the detection result storing unit 360, and the detection result storing unit 360 feeds back the detection result to the upper computer 20 through the communication unit 350. Illustratively, the test data is buffered in DDR3 of 2GB in the test process, the data transmission and the command interaction are arbitrated by the priority fixed by the gigabit Ethernet 351, and the time delay of the command interaction is greatly reduced while the high-speed data transmission is ensured.
Optionally, with continued reference to fig. 2, the upper computer 20 includes a wafer detection configuration unit 210 to be tested, an automatic probe station control unit 220, and an algorithm regression control unit 230; the automatic probe station control unit 220 is configured to generate an operation instruction and a first detection instruction; the wafer inspection configuration unit 210 to be inspected is configured to generate a second inspection instruction; the algorithm regression control unit 230 is used for generating a third detection instruction.
The operation instruction is an instruction sent to the automatic probe station 10, which can make the automatic probe station 10 execute the action specified by the operation instruction, so as to assist the wafer inspection device 30 to implement the test of any March algorithm on the wafer to be inspected. The second inspection instruction is an instruction sent to the wafer inspection device 30, and can enable the wafer inspection device 30 to inspect the operation of the automatic probe station 10, that is, to confirm the connection state of the probe of the automatic probe station 10 and the position to be inspected of the wafer to be inspected. The third detection instruction is an instruction sent to the wafer detection device 30, and can enable the wafer detection device 30 to realize testing of any March algorithm on the wafer to be detected, generate a detection result, and feed back the detection result to the upper computer 20.
The algorithm regression control unit 230 has a core function of combining the March algorithm microinstruction, the test preset write data and the scan frequency to perform the regression test. The wafer inspection configuration unit 210 and the algorithm regression control unit 230 are similar, and it is guaranteed that each combination of algorithm regression can traverse each common voltage point.
The wafer detection configuration unit 210 to be tested comprises a voltage configuration subunit and a voltage monitoring subunit; the second detection instruction comprises a voltage adjustment instruction and a voltage acquisition instruction; the voltage configuration subunit is used for generating a voltage adjustment instruction, and the voltage monitoring subunit is used for generating a voltage acquisition instruction.
Specifically, the dynamic/static clock generation subunit generates a clock signal according to the voltage adjustment instruction, and the soft core 320 configures the scan voltage and the scan frequency of the wafer to be detected according to the clock signal. The wafer inspection device 30 monitors the voltage signal of the wafer to be inspected according to the voltage acquisition instruction, so as to confirm the connection state of the probe and the position to be inspected of the wafer to be inspected according to the voltage signal.
For example, if the wafer detection device 30 does not detect that the voltage signal is outside the preset threshold voltage range, it indicates that the connection state between the probe and the position to be detected of the wafer to be detected is an open circuit state or a short circuit state; if the voltage signal detected by the wafer detecting device 30 is within the preset threshold voltage range, it indicates that the connection state between the probe and the position to be detected of the wafer to be detected is a normal state.
Optionally, with continued reference to fig. 2, the upper computer 20 further includes a first data processing unit 240 and a second data processing unit 250; the first data processing unit 240 is configured to receive the detection result and pre-process the detection result; the second data processing unit 250 is configured to draw a defect bitmap according to the preprocessed detection result and the coordinates of the position to be detected, and splice the defect bitmap to obtain a wafer defect map; the second data processing unit 250 is further configured to analyze the pre-processed detection result to generate a wafer defect analysis report.
The detection result comprises three types of errors, namely address errors, data errors and algorithm error stages. The first data processing unit 240 pre-processes the detection result, i.e., classifies the detection result according to the error type. The second data processing unit 250 draws a defect bitmap for the preprocessed detection result and the coordinates of the position to be detected, splices the defect bitmap to obtain a wafer defect map, and analyzes the preprocessed detection result to generate a wafer defect analysis report.
Optionally, fig. 3 is a schematic structural diagram of another wafer inspection apparatus 30 according to the embodiment of the present invention. As shown in fig. 3, the logic is integrally implemented on the FPGA, and specifically includes an ethernet 351, a programmable memory detection unit 310, a DDR3 read/write control unit 380, a Microblaze soft core 321, a dynamic static clock 361, a multiplexing pin 322, and a data arbitration unit 370. The whole logic on the FPGA is combined with external hardware circuits (voltage control, current monitoring, debug, open-short test, etc.) to form a wafer inspection device 30 which supports any March algorithm programming test, efficient data transmission and command interaction, large-capacity test data storage, multi-voltage test, current monitoring, and open-short test.
The Microblaze soft core 321 of xilinux embedded in the FPGA system can efficiently expand the control of multiple external serial devices through the standard IP mounted on the core. After the Microblaze soft core 321 is embedded in the FPGA system, external 10 paths of i2c masters (standard IIC MASTER x 10 323), 5 paths of GPIOs (standard GPIOs x 4 324 and standard GPIOs 326) and 2 paths of UART (standard UART x 2 325) can be all mounted on the Microblaze soft core 321 (to interact information with the Microblaze soft core 321 through the AXI4-Lite interface 327). The user side can control and monitor related functions through C programming, so that the flexibility and usability of the whole system are greatly enhanced.
The operation of the wafer inspection apparatus 30 is described with reference to fig. 3: the upper computer 20 sends a first detection instruction to the Microblaze soft core 321 through the ethernet 351 and the AXI4-Lite interface 327. Microblaze soft core 321 controls the open and short circuit test to modify the operation mode of multiplexing pin 322 to the output mode and multiplexing pin 322 to output voltage through AXI4-Lite interface 327 and standard GPIO 326. At the same time, the Microblaze soft core 321 controls voltage control to detect a voltage signal of the wafer 40 to be detected through the AXI4-Lite interface 327 and the standard IIC MASTER x10 323, so as to determine the connection state of the multiplexing pin 322 and the wafer 40 to be detected. After determining the connection state between the multiplexing pin 322 and the wafer 40 to be tested, the Microblaze soft core 321 controls the open-short circuit test to modify the working mode of the multiplexing pin 322 to be an input/output mode through the AXI4-Lite interface 327 and the standard GPIO 326. In addition, the Microblaze soft core 321 controls the current signal of the wafer 40 to be detected through the AXI4-Lite interface 327 and the standard GPIO x4 324 to monitor and detect the current signal, so as to determine whether the wafer 40 to be detected works normally or not and perform power consumption statistics on the wafer 40 to be detected according to the current signal.
If the connection state between the multiplexing pin 322 and the wafer 40 to be detected is a normal state, the Microblaze soft core 321 obtains a second detection instruction and a third detection instruction from the upper computer 20 through the AXI4-Lite interface 327 and the ethernet 351, the Microblaze soft core 321 obtains a clock signal from the dynamic static clock 361 through the second detection instruction, the Microblaze soft core 321 generates a scan voltage and a scan frequency according to the clock signal, and performs voltage control through the standard IIC MASTER x 10 323, that is, performs voltage configuration on the wafer 40 to be detected. The Microblaze soft core 321 tests the wafer 40 to be tested by sending the third detection instruction to the programmable memory detection unit 310, and the detection result output by the programmable memory detection unit 310 is stored in the DDR3 control after passing through the data arbitration unit 370. DDR3 feeds back the detection result to host computer 20 via ethernet 351.
Fig. 4 is a flow chart of a wafer inspection method according to an embodiment of the present invention, where the wafer inspection method is performed by the wafer inspection system according to any embodiment of the present invention. The wafer detection method specifically comprises the following steps:
S110, the upper computer generates an operation instruction and a first detection instruction.
And S120, the automatic probe station connects the positions to be detected of the wafers to be detected on the automatic probe station according to the operation instructions.
And S130, the wafer detection device determines the connection state of the probe of the automatic probe station and the position to be detected of the wafer according to the first detection instruction.
And S140, the upper computer generates a second detection instruction and a third detection instruction according to the connection state.
S150, the wafer detection device configures a wafer to be detected according to the second detection instruction;
And S160, the wafer detection device detects the wafer to be detected according to the third detection instruction and generates a detection result.
S170, analyzing the detection result by the upper computer, drawing a wafer defect map and generating a wafer defect analysis report.
According to the embodiment of the invention, the upper computer generates the operation instruction and the first detection instruction; the automatic probe station connects the positions to be detected of the wafers to be detected on the automatic probe station according to the operation instructions; the wafer detection device determines the connection state of the probe of the automatic probe station and the position to be detected of the wafer according to the first detection instruction; the upper computer generates a second detection instruction and a third detection instruction according to the connection state; the wafer detection device configures a wafer to be detected according to the second detection instruction; the wafer detection device detects the wafer to be detected according to the third detection instruction and generates a detection result; and the upper computer analyzes the detection result and draws a wafer defect map and a wafer defect analysis report. Therefore, the method and the device can realize the test of any March algorithm on the wafer, further combine the wafer defect coordinates and the wafer defects to generate a wafer defect analysis report, and provide comprehensive and effective data for the improvement scheme for improving the yield of the wafer production line.
Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as provided by any of the embodiments of the present invention.
The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. Computer-readable storage media include (a non-exhaustive list): an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access Memory (Random Access Memory, RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (ELECTRICALLY ERASABLE, programmable Read-Only Memory, EPROM), a flash Memory, an optical fiber, a portable compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with computer readable program code embodied in the data signal. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++, ruby, go and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network, LAN) or a wide area network (Wide Area Network, WAN), or may be connected to an external computer (e.g., through the internet using an internet service provider).
It will be appreciated by those skilled in the art that the term user terminal encompasses any suitable type of wireless user equipment, such as a mobile telephone, a portable data processing device, a portable web browser or a car mobile station.
In general, the various embodiments of the invention may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto.
Embodiments of the invention may be implemented by a data processor of a mobile device executing computer program instructions, e.g. in a processor entity, either in hardware, or in a combination of software and hardware. The computer program instructions may be assembly instructions, instruction set architecture (Instruction Set Architecture, ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.
The block diagrams of any of the logic flows in the figures of this invention may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read Only Memory (ROM), random Access Memory (RAM), optical storage devices and systems (digital versatile disk DVD or CD optical disk), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general purpose computers, special purpose computers, microprocessors, digital signal processors (DIGITAL SIGNAL Processing, DSP), application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic devices (Field-Programmable GATE ARRAY, FPGA), and processors based on a multi-core processor architecture.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. The wafer detection system is characterized by comprising an automatic probe station, an upper computer and a wafer detection device;
The automatic probe station and the wafer detection device are connected with the upper computer, and the automatic probe station is connected with the wafer detection device;
the upper computer is used for generating an operation instruction and a first detection instruction;
The automatic probe station is used for connecting the position to be detected of the wafer to be detected on the automatic probe station according to the operation instruction; the wafer detection device is used for determining the connection state of the probe of the automatic probe station and the position to be detected of the wafer to be detected according to the first detection instruction; the upper computer is used for generating a second detection instruction and a third detection instruction according to the connection state, the wafer detection device is used for configuring the wafer to be detected according to the second detection instruction, and the wafer detection device is used for detecting the wafer to be detected according to the third detection instruction and generating a detection result; the upper computer is used for analyzing the detection result, drawing a wafer defect map and generating a wafer defect analysis report.
2. The wafer inspection system of claim 1, wherein the automated probe station comprises a probe cleaning unit, a probe connection unit, a wafer control unit, and a coordinate positioning unit;
The probe cleaning unit is used for performing needle cleaning operation according to the operation instruction;
The probe connection unit is used for performing probe connection operation according to the operation instruction;
the wafer control unit is used for controlling the probe to be adjusted to a position to be detected according to the operation instruction;
The coordinate positioning unit is used for determining the coordinate of the detection position according to the operation instruction.
3. The wafer inspection system of claim 1, wherein the wafer inspection device comprises a programmable memory inspection unit, a soft core, an open-short test control unit, a clock signal generation unit, and a communication unit;
The soft core is used for acquiring the first detection instruction through the communication unit, and the open-short circuit test control unit is used for determining the connection state of the probe and the position to be detected of the wafer to be detected according to the first detection instruction; the soft core is further used for acquiring a second detection instruction and a third detection instruction through the communication unit according to the connection state, the clock signal generating unit is used for generating a clock signal according to the second detection instruction, and the soft core is used for configuring the wafer to be detected according to the clock signal; the programmable memory detection unit is used for detecting the wafer to be detected according to the third detection instruction and obtaining a detection result.
4. The wafer inspection system of claim 3 wherein the clock signal generation unit comprises a dynamic/static clock generation subunit;
the dynamic/static clock generation subunit is used for generating a clock signal, and the soft core is used for configuring the scanning voltage and the scanning frequency of the wafer to be detected according to the clock signal.
5. The wafer inspection system of claim 3, wherein the wafer inspection apparatus further comprises an inspection result storage unit;
the detection result storage unit is used for storing the detection result and sending the detection result to the upper computer through the communication unit.
6. The wafer inspection system of claim 1, wherein the upper computer comprises a wafer inspection configuration unit to be inspected, an automatic probe station control unit, and an algorithm regression control unit;
The automatic probe station control unit is used for generating the operation instruction and the first detection instruction;
The wafer detection configuration unit to be detected is used for generating the second detection instruction;
The algorithm regression control unit is used for generating the third detection instruction.
7. The wafer inspection system of claim 6, wherein the wafer inspection configuration unit to be inspected comprises a voltage configuration subunit and a voltage monitoring subunit;
The second detection instruction comprises a voltage adjustment instruction and a voltage acquisition instruction; the voltage configuration subunit is used for generating a voltage adjustment instruction, and the voltage monitoring subunit is used for generating a voltage acquisition instruction.
8. The wafer inspection system of claim 6, wherein the upper computer further comprises a first data processing unit and a second data processing unit;
The first data processing unit is used for receiving the detection result and preprocessing the detection result;
The second data processing unit is used for drawing a defect bitmap for the preprocessed detection result and the coordinates of the position to be detected, and splicing the defect bitmap to obtain a wafer defect map;
the second data processing unit is further used for analyzing the detection result after pretreatment and generating a wafer defect analysis report.
9. A wafer inspection method performed by the wafer inspection system of any one of claims 1-8, comprising:
the upper computer generates an operation instruction and a first detection instruction;
the automatic probe station connects the position to be detected of the wafer to be detected on the automatic probe station according to the operation instruction;
the wafer detection device determines the connection state of the probe of the automatic probe station and the position to be detected of the wafer according to the first detection instruction;
The upper computer generates a second detection instruction and a third detection instruction according to the connection state;
the wafer detection device configures the wafer to be detected according to the second detection instruction;
the wafer detection device detects the wafer to be detected according to the third detection instruction and generates a detection result;
and the upper computer analyzes the detection result, draws a wafer defect map and generates a wafer defect analysis report.
10. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the wafer inspection method of claim 9.
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